Panasonic JB-3300 Technical Manual page 216

(6)
(7)
*STPDT
*STPCD
DATA
*ESTB
EBUSY
*EACK
Interrupt enable circuit
Interrupt enable or disable to the CPU is selected by Bit 4, INT
EN, of the I/O address 37A (HEX). For an interrupt, an
interrupt request to the interrupt controller is generated by
the *EACK signal of the printer using IRQ7.
Data output timing
Figure 5-67 shows data output timing to the printer and printer
response timing.
Figure 5-67 Parallel Interface Timing Chart
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