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(a)
Data bus transceiver
The data bus transceiver is a bidirectional buffer that connects the
CPU data bus (DBO to DB7) with the main memory/display data bus (VDO
to VD7).
Figure 5-23
Data Bus Transceiver Circuit
The data bus transceiver functions only in the following three cases:
(1)
When the main memory is accessed
(2)
When data is written in VRAM
(3)
When the CPU reads the CRTC register
The direction of data flow through the data bus transceiver is
determined as follows:
|
Memory access by CPU:
From VD bus to DB bus
T/O read by CPU:
From VD bus to DB bus
Any other time:
From DB bus to VD bus
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Troubleshooting
