Panasonic JB-3300 Technical Manual page 268

As waS previously mentioned, the X lines are sequentially scanned from
above and a voltage of -200 V is applied. When the output transistors are
OFF, the voltage is maintained at -95 V by the prebias resistors. The
reset electrode XR is connected to the left and right driver circuits and
remains ON for a period twice that of the other X lines, thus ensuring
reset-discharging.
The following paragraph explains the operation of the display circuit,
composed of Y driver circuits (Figure 4-2), during the horizontal scanning
period (Figure 4-4).
First, the 4-bit parallel display data bits DAO through DA3 are trans-
mitted to the upper and lower 320-bit shift registers as 160 Y line data
by the shift clock pulse SCLK. Then, the 640-bit display data of the
shift registers is fetched to the latches at the trailing edge of the
strobe STB. The blanking periods, tBn-1, tBn, ..., during which all the X
lines are OFF, are provided within the respective horizontal scanning
periods tHn-1, tHn, .... During these periods, the charge CHG forcibly
switches the output transistors of the Y drivers to ON and charges the
auxiliary discharge capacitors installed on each of the Y lines in the
display panel.
Then, if, for example, Xn is switched ON when the latch output connected
to Ym is "L" (LOW), the output transistor is switched OFF, and trigger
Signal is discharged based on the charge of the trigger capacitor
(indicated by the broken lines in Figure 4-4). If this latch output is
"H" (HIGH), the output transistor is switched ON, effecting a display
discharge in which a fixed discharge current flows, constrained by the
resistance RA. During this period, if the clear CL is made variable by
means of the external volume, as shown in Figure 4-4, the output
transistor is turned OFF regardless of the latch output, thus effecting
luminance control. The discharge period is prolonged in the order Q),
@ 1 and the luminance rises, becoming 100% in the state indicated
by .
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