Panasonic JB-3300 Technical Manual page 232

5.13 Option Slot Interface
(a) The circuit shown in Figure 5-80 has two main circuits; one applied
(1) af the option slot of the equipment is used and the other, (2) if
the option slot of the extension unit is used.
The circuit delays the generation of data bus gate and DIR signals by
150 ns if the option slot of the extension unit is used. This is
because data input/output is delayed by 150 ns in the receiver card
provided in the extension unit.
KEDGATE (X4F }
EDOIR (X4F)
KEDACK 2(X5E;
— a =e ame ae ae cee oem ee ee oe oe eam
(X2E)EXRESET
us
KINTIO (X2F)
(X2F) XEXPDCS
(ASO) EALE
(X50) X% EMEMR
(X50) X EIOR
(KX7A) X EXTMEM
(2-1OF )XEINTIO
Figure 5-80
(b) Description of circuit
(1) The 74LS74 (11B-1) generates a select signal to switch the gate
and DIR signals of the data bus.
This signal is input to the select signal of the 74LS253.
(2) The 74LS253 (7C) is used to switch a gate and DIR signals if the
option slot of the equipment is used or the 150-ns deiayed gate
and DIR signals if the option slot of the extension unit is
used.
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