Panasonic JB-3300 Technical Manual page 225

(1) FDD control command register
The circuit consists of the FDD control command register, drive
select decoder, and buffer.
Command Register Drive Selector Decorder
(X4CXX4E) Pao +
XDMAGATE | 7438x4
PO" L868 7
I
(X3B) DO4~DO0
XDRIVE SEL4
XDRIVE SEL53
(X3A) DO7T~ DO5
ee ee
XORIVE SEL2
(KX3D) XFDDCS
(X3C)XXIOW
(K3C) XRESET
XDRIVE SEL!
{
TE gLle
UPD765A, L832. | tS XMOTOR ON
LSo4 Looe\
Buffer
Figure 5-75 FDD Control Command Buffer Register Circuit
MSB LSB
DO7 6 5 4 3 2 1 DOO
. 4 4 DOO DO1| Drive No.
L__. DRIVE SELECT 0 0 1
0 1 2
FDC RESET 1 0 3
Low active 1 1 4
- INTERRUPT/DMA REQUEST ENABLE
High active
MOTOR ENABLE
x: Do not care
DO4 DO5| DOG} DO76| * Motor on
The motor rotates when any
0 bit from DO4 to DO7 is on.
(Low active)
IIT - 105