Panasonic JB-3300 Technical Manual page 184

(4) RAS, CAS timing circuit
The RAS, CAS timing circuit controls the RAS and CAS signals of
VRAM according to the VRAM access timing. In the CRT cycle
mode, the circuit performs a page mode read on RAM. In the CPU
cycle mode, it performs a read or early write. Ina refresh
cycle, it performs a RAS-only refresh. Figure 5-40 shows the
RAS, CAS timing circuit.
(3G) CLK4
(3C) ADV CRT
(3F) XCLK2
(3F)CLK2
(7H) EN EVEN
(2G) BASIC-CLK
(3F)CLKI
(30) XCPU ADR
(3G) XCLK3
(3C)CRT ADR
(3F) XCLKI
(3G )CLK3
(7-1D0)(100)(7F) EN EVEN
XRAS (6B)
(RAS)
$175(4/4)
MUX (4A)
S175 (3/4) |
[cas]
CPU CAS (5-7C)
V1
XCPU CAS (5- 6B)
XCAS (6B)
XCRT CASO(7C)
CRT CASO (4H)
XCRT CASI(7C)
Figure 5-40 RAS, CAS Timing Circuit
If