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(b)
VRAM data latch
When the CPU or DMAC reads VRAM, the data read out from VRAM onto the
data bus is latched.
Then the CPU (or DMAC)
stops reading VRAM and
begins reading the succeeding display data.
The latched data is held
on the DB data bus until the CPU (or DMAC)
finishes the read.
Figure
5-24 shows the data latch timing.
* eee
|
*MEMR
*CPU CAS
|
|
VDO to 7
<Valid >
7
(ore
/
\
DBO to 7
{
old
Data
X Valid )
Figure 5-24
Data Latch Timing Chart
Display Mode Register
The 6-bit Display Mode register sets the display mode of the plasma
display panel.
The Display Mode register is cleared by the *RESET
signal when power is turned on.
The display mode is set to TEXT
40x25.
If - 50
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