Ddr Unused Pins; Dynamic Memory Implementation - Xilinx Zynq-7000 Design Manual

Table 5-4: DDR Interface Signal Pins (Cont'd)
Pin Name
DDR_DQ[31:0]
DDR_DM[3:0]
DDR_DQS_P[3:0]
DDR_DQS_N[3:0]
DDR_VRP
DDR_VRN
DDR_VREF[1:0]
Unused DDR pins should be connected as shown in
For designs utilizing single-ended DQS, connect the DQS signal to DQS_P. DQS_N can either
be connected to the DQS_B I/O of the SDRAM, or via resistor divider to VCCO/2.
Table 5-5: DDR Unused Pins
Unconnected Pins
DDR Unused Pins, x16 non-ECC
O
DQ/DQS IO
IO
DDR Unused Pins, x16 ECC
O
DQ/DQS IO
Other IO

Dynamic Memory Implementation

Figure 5-5, Figure 5-6
typical boards.
Zynq-7000 PCB Design Guide
UG933 (v1.8) November 7, 2014
Chapter 5: Processing System (PS) Power and Signaling
Direction
I/O Data
O Data mask
I/O Differential data strobe positive
I/O Differential data strobe negative
I/O Used to calibrate input termination
I/O Used to calibrate input termination
I/O Reference voltage
Comments
Unconnected
Unconnected, internal pull-up by software
Unconnected, internal pull-up by software
Unconnected
Connect to SDRAM
Unconnected, internal pull-up by software
and Figure 5-7 show examples of implementing DDR memory on
www.xilinx.com
Description
Table 5-5.
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