Ap Soc Mounting Inductance; To Reduce Parasitic Inductance - Xilinx Zynq-7000 Design Manual

between power and ground planes decreases, the value of this capacitance increases.
Capacitance per square inch is shown in
arising from these PCB power-ground plane pairs is generally inconsequential, given the
substrate decoupling capacitors present in Zynq-7000 AP SoC devices.

AP SoC Mounting Inductance

The PCB solder lands and vias that connect the AP SoC power pins (V
contribute an amount of parasitic inductance to the overall power circuit. For existing PCB
technology, the solder land geometry and the dogbone geometry are mostly fixed, and
parasitic inductance of these geometries does not vary. Via parasitic inductance is a
function of the via length and the proximity of the opposing current paths to one another.
The relevant via length is the portion of the via that carries transient current between the AP
SoC solder land and the associated V
power plane and the PCB backside) does not affect the parasitic inductance of the via (the
shorter the via between the solder lands and the power plane, the smaller the parasitic
inductance). Parasitic via inductance in the AP SoC mounting is reduced by keeping the
relevant V and GND planes as close to the AP SoC as possible (close to the top of the PCB
CC
stackup).
Device pinout arrangement determines the proximity of opposing current paths to one
another. Inductance is associated with any two opposing currents (for example, current
flowing in a V
CC
two opposing paths reduces the loop's total inductance. Therefore, when given a choice,
V and GND vias should be as close together as possible.
CC
The via field under an AP SoC has many V
function of the proximity of one via to another:
• For core V
CC
GND pins.
• For I/O V
CC
path, whether carried by a V

To reduce parasitic inductance:

• Core V pins such as V
CC
the pinout.
• V and GND pins are distributed among the I/O pins.
CCO
Every I/O pin in the Zynq-7000 AP SoC device pinout is adjacent to a return-current pin.
AP SoC pinout arrangement determines the PCB via arrangement. The PCB designer cannot
control the proximity of opposing current paths but has control over the trade-offs between
the capacitor's mounting inductance and AP SoC's mounting inductance:
Zynq-7000 PCB Design Guide
UG933 (v1.8) November 7, 2014
CC
and GND via pair). A high degree of mutual inductive coupling between the
supplies (V and V
CCINT
supplies (V ), opposing current is between any I/O and its return current
CCO
or GND pin.
CCO
and V
CCINT
www.xilinx.com
Chapter 3: Power Distribution System
Table 3-4. However, the amount of capacitance
or GND plane. Any remaining via (between the
and GND vias, and the total inductance is a
CC
), opposing current is between the V
CCAUX
are placed in a checkerboard arrangement in
CCAUX
and GND)
CC
and
CC
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