Dynamic Memory; Ddr Interface Signal Pins; Setting Mode Pins - Xilinx Zynq-7000 Design Manual

X-Ref Target - Figure 5-4

Dynamic Memory

Zynq-7000 AP SoC devices support DDR2, DDR3/3L, and LPDDR2 (mobile DDR) dynamic
memory. The memory is connected to dedicated pins in I/O Bank 502. This bank has
dedicated I/O, termination, and reference voltage supplies.
DDR runs at very high speeds and special care need to be taken in board layout to ensure
signal integrity. The following sections show the recommendations for DDR memory
designs for Zynq-7000 AP SoC devices.

DDR Interface Signal Pins

Table 5-4 lists all dynamic memory interface signals in Bank 502.
Table 5-4: DDR Interface Signal Pins
Pin Name
DDR_CK_P
DDR_CK_N
DDR_CKE
DDR_CS_B
DDR_RAS_B
DDR_CAS_B
DDR_WE_B
DDR_BA[2:0]
DDR_A[14:0]
DDR_ODT
DDR_DRST_B
Zynq-7000 PCB Design Guide
UG933 (v1.8) November 7, 2014
Chapter 5: Processing System (PS) Power and Signaling
V
CCO_MIO0
1
2
20 KΩ
3
GND
Figure 5-4: Setting Mode Pins
Direction
O Differential clock output positive
O Differential clock output negative
O Clock enable
O Clock select
O RAS row address select
O CAS column address select
O Write enable
O Bank address
O Address
O Output dynamic termination
O Reset
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