Ddr3/3L Board Implementation - Xilinx Zynq-7000 Design Manual

X-Ref Target - Figure 5-5
VREF VDDQ
VREF VDDQ
Addr, Command, Contrl
(Addr, we_b,
ras_b, cas_b,
odt, cs_b)
CLK_P
CLK_N
CKE
DRST_B
ZYNQ
Data Group 0
Rdown
(dq, dqs, dm)
Data Group 1
(dq, dqs, dm)
Data Group 2
(dq, dqs, dm)
Data Group 3
(dq, dqs, dm)
Rvrnp
VRN
VRP
Rvrnp
Zynq-7000 PCB Design Guide
UG933 (v1.8) November 7, 2014
VREF VDDQ VREF
VREF VDDQ VREF
Addr, Command, Addr, Command,
Contrl
(Addr, we_b, (Addr, we_b,
ras_b, cas_b, ras_b, cas_b,
odt, cs_b) odt, cs_b)
clk clk
Cke Cke
rset_b rset_b
DDR3
DDR3
Data Group
ZQ Rzq
(dq, dqs, dm)
Data Group
(dq, dqs, dm)
DDR
Termination
Regulator
VDDQ
VDDQ
Figure 5-5: DDR3/3L Board Implementation
www.xilinx.com
Chapter 5: Processing System (PS) Power and Signaling
VDDQ VREF VDDQ
VDDQ VREF VDDQ
Addr, Command,
Contrl Contrl
(Addr, we_b,
ras_b, cas_b,
odt, cs_b)
clk
Cke
rset_b
DDR3
ZQ Rzq
Data Group
(dq, dqs, dm)
VREF
VREF
VTT
VTT
VREF VDDQ
VDDQ VTT
VREF
Addr, Command,
Contrl
(Addr, we_b,
ras_b, cas_b,
odt, cs_b)
clk
Cke
rset_b
VTT
DDR3
ZQ Rzq
Data Group
(dq, dqs, dm)
ZQ Rzq
UG585_c30_04_022814
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Rterm
Rclk
Rterm
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