Input Thresholds; Topographies And Termination - Xilinx Zynq-7000 Design Manual

Some I/O standards have attributes to control drive strength and slew rate, as well as the
presence of weak pull-up or pull-down and weak-keeper circuits (not intended for use as
parallel termination). Drive strength and slew rate can be used to tune an interface for
adequate speed while not overdriving the signals. Weak pull-ups, weak pull-downs, and
weak keepers can be used to ensure a known or steady level on a floating or 3-stated signal.
The "SelectIO Resources" chapter of UG471, 7 Series FPGAs SelectIO Resources User Guide
describes which standards support these attributes. Refer to this user guide for more
information.
LVCMOS, when set to 6 mA DRIVE and FAST slew, has an approximate output impedance
close to 50Ω , allowing it to be used as a crude approximation of a controlled-impedance
driver. The impedance match of the weak driver to the transmission line is only approximate
and varies with voltage and temperature.

Input Thresholds

The input circuitry of the single-ended standards fall into two categories: those with fixed
input thresholds and those with input thresholds set by the V
has three advantages:
• It allows for tighter control of input threshold levels
• It removes dependence on die GND for the threshold reference
• It allows for input thresholds to be closer together, which reduces the need for a large
voltage swing of the signal at the input receiver
Two 1.8V I/O standards that illustrate this are LVCMOS18 and SSTL18 Class 1. The
thresholds for 1.8V LVCMOS are set at 0.63V and 1.17V (necessitating that the signal at the
receiver swing a full 540 mV at minimum to make a logic transition). The thresholds for
SSTL18 Class 1 are set at V
at 0.775V and 1.025V (necessitating that the signal at the receiver only swing 250 mV at
minimum to make a logic transition). This smaller required swing allows for higher
frequency of operation in the overall link. A smaller swing at the driver means reduced DC
power is required with less transient current. A historical drawback to the use of V
that the semi-dedicated V
standard was used in a bank that required the V
devices, the reference voltage can either be provided using the semi-dedicated V
optionally generated internally using the Internal V
SelectIO User Guide for more details on Internal V
decoupling and decoupling of all other supplies, see

Topographies and Termination

Topography generally refers to the arrangement of drivers, receivers, interconnect and
terminations in an interface. The techniques used in unidirectional topographies are
different from those used in bidirectional topographies, so these are treated separately.
Zynq-7000 PCB Design Guide
UG933 (v1.8) November 7, 2014
– 0.125V and V + 0.125V, or for a nominal V
REF REF
pins of the bank could not be used as I/Os whenever an I/O
REF
REF
www.xilinx.com
Chapter 4: SelectIO Signaling
voltage. The use of V
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supply. However, with the 7 series
feature. See UG471, 7 Series FPGAs
REF
. For more information on V
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Chapter 3, Power Distribution
Send Feedback
REF
of 0.9V, set
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was
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pins, or
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System.
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