Revision History - Xilinx Zynq-7000 User Manual

Revision History

The following table shows the revision history for this document.
Date Version
06/21/2012 1.0
10/08/2012 2.0
Zynq-7000 AP SoC ZC702 Base TRD
UG925 (v6.0) February 21, 2014
Initial Xilinx release.
Updated for ISE® Design Suite 14.2.
Replaced AXI VTC with VTC throughout. Changed Sobel engine to Sobel filter.
Chapter 1, Introduction: Added R, RW, COR, SoC, and SC to
descriptions of the TRD. Updated the block diagram in
Chapter 2, Functional Description: In
with a dotted line for Monitor and between VIDEO_MUX0 and Clk_detect and
revised AXI Interconnect inputs. Added slice registers to
changed SOBEL_ENGINE to FILTER_VDMA and FILTER_ENGINE. Added
FILTER_0_interrupt row in
FILTER_VDMA. In Table 2-4, GPIO bit number 7 became N/A. In
page 19, (FCLKCLK[3:0]) became (FCLK_CLK). In
(FCLKRESETN[3:0]) became FCLK_RESET[3:0]_N and FCLKRESETN[0] changed to
FCLK_RESET0_N. In Clocking, page
In Table 2-5, clock signal sources and uses were updated. In
xFilter, changed frequency and connection of s_axi_CONTROL_BUS_ACLK and
deleted s_axi_SOBEL_CONTROL_ACLK. Changed frequency of
INTERCONNECT_ACLK bus. Changed SOBEL_ENGINE to FILTER_ENGINE and
SOBEL_VDMA to FILTER_VDMA. Added information to the end of the table for
DVI2AXI_0, CRESAMPLE_0, and YUV2RGB_0 components. In
Reset Module, page 22, input to the proc_sys_reset core is generated by PS
Proc_sys_reset_1_N. In Clock Detect, page
The v_cresample, v_ycrcb2rgb, vsrc_sel, sobel_filter_top, and dvi2axi sections
were added. Starting in fmc imageon hdmi in, page
YCrCb. In Figure 2-4, added xFilter to the Device Drivers. In the Boot Loader
section, removed "HDMI in" chip. In
text for clarity and reformatted the IOTCL arguments. Modified the description
of Figure 2-6 for clarity. Modified the descriptions of
for clarity and added description of cases 4, 5, and 6. Modified
Filter Processing, page 45
page 33. Figure 2-4, GUI for TRD Application was replaced and notes about the
GUI were added. AXI was added to the Plot Graph descriptions. DDR3 was
removed from Figure 2-8
page 45 description and API changed.
Appendix A, Register Description: New sections were added from
Registers, page 46 to the end of the appendix. Removed redundant instances of
TPG.
Appendix C, Directory Structure:
Appendix F, Additional Resources: PG012, LogiCORE IP Chroma Resampler
Product Guide and PG014, LogiCORE IP YCrCb to RGB Color-Space Converter
Product Guide were added to references.
Appendix G, Regulatory and Compliance Information
Appendix H, Warranty was added.
www.xilinx.com
Revision
Figure 2-1, replaced the continuous line
Table 2-3, and SOBEL_VDMA changed to
PL Reset, page
19, PS FCLKCLK[0] changed to PS FCLK_CLK0.
23, FMC changed to FMC-IMAGEON.
xFilter, page 30, updated the introductory
for clarity. Added xFilter sections to
and Figure 2-9. The Software Sobel Filter Processing,
Figure C-1, Directory Structure, was updated.
Table 1-1. Expanded
Figure 1-1.
Table 2-1. In Table 2-2,
PL Clocks,
19,
Table 2-9, added
Processor System
25, YCbCr was changed to
Figure 2-8 and Figure 2-9
Software Sobel
Xilinx Linux Kernel,
Sobel Filter
was added.
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