Ddr2 Board Implementation - Xilinx Zynq-7000 Design Manual

X-Ref Target - Figure 5-6
VREF VDDQ
VREF VDDQ
Data Group 0
(dq, dqs, dm)
Data Group 1
(dq, dqs, dm)
Cke
ZYNQ
CLK_P
CLK_N
Addr, Command, Contrl
(Addr, we_b, ras_b,
cas_b, cs_b)
ODT
Data Group 2
(dq, dqs, dm)
Data Group 3
(dq, dqs, dm)
VRN
VRP
Zynq-7000 PCB Design Guide
UG933 (v1.8) November 7, 2014
Chapter 5: Processing System (PS) Power and Signaling
VREF
VREF
Data Group
(dq, dqs, dm)
Addr, Command, Contrl (Addr,
CLK
we_b, ras_b, cas_b, odt, cs_b)
cke _P_N
Rdown
VTT
Rterm
cke CLK Addr, Command, Contrl (Addr,
_P_N we_b, ras_b, cas_b, odt, cs_b)
Rdown
Data Group
(dq, dqs, dm)
VDDQ
Rvrnp
VDDQ
VDDQ
Rvrnp
Figure 5-6: DDR2 Board Implementation
www.xilinx.com
VDDQ
Data Group
VDDQ
(dq, dqs, dm)
DDR2
_P_N
cke
cke
_P_N
DDR2
Data Group
(dq, dqs, dm)
VREF VDDQ
VREF VDDQ
DDR
Termination
Regulator
VREF
VREF
VTT
VTT
VREF VDDQ
VREF VDDQ
DDR2
CLK Addr, Command, Contrl (Addr,
we_b, ras_b, cas_b, odt, cs_b)
Rclk
CLK Addr, Command, Contrl (Addr,
we_b, ras_b, cas_b, odt, cs_b)
DDR2
VREF VDDQ
VREF VDDQ
UG933_c5_05_020614
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