Revision History - Xilinx Zynq-7000 Design Manual

Revision History

The following table shows the revision history for this document.
Date Version
06/04/2012 1.0
06/06/2012 1.1
08/29/2012 1.2
10/11/2012 1.2.1
11/05/2012 1.2.2
02/12/2013 1.3
04/01/2013 1.4
09/26/2013 1.5
Zynq-7000 PCB Design Guide
UG933 (v1.8) November 7, 2014
Initial Xilinx release.
Corrected format issue.
Updated Table 3-1 and Table 3-2
capacitor specification to
Corrected document number (changed UG993 to UG933).
Corrected sizing problem in PDF (no content change).
(2)
Added Note to Table 3-2. Added suggested part numbers to
paragraph under V
CCPAUX
V – PS PLL Supply. Added
CCPLL
added last sentence under
Voltage. Modified CAUTION! under
Mode and Note under DDR Supply
pull-down resistor to a pull-up resistor in
entire MIO/EMIO IP Layout Guidelines
Added XC7Z100 devices to
Table 3-3. Changed "0805 Ceramic Capacitor" section heading to
Frequency Capacitors and modified first paragraph. Removed dimensions, changed
"0805" to "0402" in Figure 3-1
Deleted last sentence under
"maximum" in third sentence of second paragraph under
Added second to last sentence under
Reference Voltage. Changed "Rup" to "Rterm" in
Drst_b from Figure 5-6 and
pull-down resistor in Figure
N/A. Updated values in first row of
to "two" under DDR Routing
Table 5-12. Deleted "NAND (ONFI)," "NOR/Flash/SRAM," "SPI Master," "SWDT (System
Watch Dog Timer)," and "TTC (Triple Time Counter" subsections from
Layout Guidelines and modified remaining subsections. Changed "EN208" to "EN247"
and "DS821" to "PG054" under
Added XC7Z010, XC7Z015, and XC7Z030 packages/devices to
Changed suggested part number for the 4.7 µF capacitor in
unused pins to Table 5-5. Modified
resistor Rdown instead of VTT via Rterm). Expanded first paragraph under
Termination. Clarified DDR Termination
Routing Topology section. Deleted SD/SDIO Peripheral Controller section. Added last
sentence under sections IIC
Chapter 6, Migration from XC7Z030-SBG485 to XC7Z015-CLG485
www.xilinx.com
Revision
for additional devices/packages. Added 680 µF
Table 3-3.
– PS Auxiliary Logic Supply. Modified paragraph under
Figure 5-3. Modified second to last sentence and
PS_DDR_VREF0, PS_DDR_VREF1 – PS DDR Reference
Configuring the V
Voltages. Changed Cke connection from a
Figure 5-5
section.
Table 3-1 and Table 3-2. Updated ESR range values in
and deleted "0402 Ceramic Capacitor" subsection.
, Modes and Attributes. Changed "minimum" to
PS_DDR_VREF0, PS_DDR_VREF1 – PS DDR
Figure 5-5
Figure 5-7. Changed Rup pull-up resistor to Rdown
5-7. Changed LPDDR2 setting in last row of
Table 5-9. Changed "Three" different topologies
Topology. Removed Fly-by topology from
Additional Resources and Legal Notices in Appendix
Figure 5-6 (Cke pins are now applied to GND via
paragraph. Added fly-by routing to
and SDIO and second sentence under QSPI. Added
Table 3-3. Modified
, V Voltage
CCO_MIO0 CCO_MIO1
through Figure 5-7. Updated
Mid and High
V – PS PLL Supply.
CCPLL
and Figure 5-6. Deleted
Table 5-6
Figure 5-8
MIO/EMIO IP
Table 3-1 and Table
Table 3-3. Added DDR ECC
DDR
DDR
Devices.
Send Feedback
to
and
A.
3-2.
2