Ddr Termination; Ddr Trace Length; Ddr Max Trace Length - Xilinx Zynq-7000 Design Manual

Table 5-6: DDR Voltage (Cont'd)
Voltage LPDDR2
V V /2
TT DDQ
PS_DDR_V
REF0
PD_DDR_V V /2
REF1 DDQ
V
REF

DDR Termination

For better signal integrity, DDR2 and DDR3 clock, address, command and control signals
need to be terminated. For DDR2, ODT and CKE are not terminated and should be pulled
down during memory initialization with a 4.7 kΩ resistor to GND. For DDR3, the DRST_B
signal is not terminated and should be pulled down during memory initialization with a
4.7 kΩ resistor to GND.
LPDDR2 does not require termination.
Table 5-7 shows the DDR termination requirements.
Table 5-7: DDR Termination
Termination LPDDR2
Rterm N/A
Rclk N/A
Rdown 4.7 KΩ
DDR3 memory also supports terminated DQS signals through the TDQS_P and TDQS_N pins.
Note:
This feature is not supported on Zynq-7000

DDR Trace Length

All DDR memory devices should be placed as closely to the Zynq-7000 AP SoC device as
possible. Table 5-8
Table 5-8: DDR Max Trace Length
Signal Group
Data Group
Address, Command, Control
Notes:
1. A guard-band is a ring of copper driven by a low-impedance source to the same voltage as the high impedance node. It is
used to protect against surface leakage currents.
Zynq-7000 PCB Design Guide
UG933 (v1.8) November 7, 2014
Chapter 5: Processing System (PS) Power and Signaling
DDR2 DDR3
V /2 V /2
DDQ DDQ
V /2 V /2
DDQ DDQ
DDR2 DDR3/3L
50Ω 40Ω
100Ω 80Ω
4.7 KΩ 4.7 KΩ
AP SoC
shows the maximum recommended trace lengths for DDR signals.
LPDDR2 DDR2
2"
1.5"
5"
3"
1.5"
5"
www.xilinx.com
DDR3L
V /2
DDQ
Use a DDR termination regulator or a
resistor voltage divider to generate V
V /2
V
DDQ
REF
Comments
There is no DDR_DRST_B in LPDDR2/DDR2 device
side
devices and those pins should be left floating.
DDR3/3L
2" Without guard-band
5" With guard-band
3" Without guard-band
5" With guard-band
Comments
and
TT
Comments
(1)
(1)
62
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