Sdr Versus Ddr Interfaces; Single-Ended Signaling; Modes And Attributes - Xilinx Zynq-7000 Design Manual

the V threshold, the state is considered Low. TTL is one common example of a
IL
single-ended I/O standard.
To reach higher interface speeds and increase noise margin, some single-ended I/O
standards rely on a precise dedicated local reference voltage other than GND. HSTL and
SSTL are examples of I/O standards that rely on a V
thought of as a fixed comparator input.
Higher-performance interfaces typically make use of differential signaling – a convention
that transmits two complementary signals referenced to one another. In differential
interfaces, a signal's assertion (whether it is High or Low) is based on the relative voltage
levels of the two complementary signals. When the voltage of the P signal is higher than the
voltage of the N signal, the state is considered High. When the voltage of the N signal is
higher than the voltage of the P signal, the state is considered Low. Typically the P and N
signals have similar swing, and have a common-mode voltage above GND (although this is
not always the case). LVDS is one common example of a differential I/O standard.

SDR versus DDR Interfaces

The difference between Single Data Rate (SDR) and Double Data Rate (DDR) interfaces has
to do with the relationship of the data signals of a bus to the clock signal of that bus. In SDR
systems, data is only registered at the input flip-flops of a receiving device on either the
rising or the falling edge of the clock. One full clock period is equivalent to one bit time. In
DDR systems, data is registered at the input flip-flops of a receiving device on both the
rising and falling edges of the clock. One full clock period is equivalent to two bit times. The
distinction of SDR and DDR has nothing to do with whether the I/O standard carrying the
signals is single-ended or differential. A single-ended interface can be SDR or DDR, and a
differential interface can also be SDR or DDR.

Single-Ended Signaling

A variety of single-ended I/O standards are available in the Zynq-7000 AP SoC I/O. For a
complete list of supported I/O standards and detailed information about each one, refer to
the "SelectIO Resources" chapter of UG471, 7 Series FPGAs SelectIO Resources User Guide.
Tables at the end of this chapter summarize for each supported I/O standard which ones
support DRIVE and SLEW attributes, bidirectional buffers, and the DCI options. It also
describes which I/O standards are supported in the high-performance (HP) and high-range
(HR) I/O banks.

Modes and Attributes

Some I/O standards can be used only in unidirectional mode, while some can be used in
bidirectional mode or unidirectional mode.
Zynq-7000 PCB Design Guide
UG933 (v1.8) November 7, 2014
to resolve logic levels. V
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Chapter 4: SelectIO Signaling
can be
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