Software Architecture - Xilinx Zynq-7000 User Manual

the gradient is computed. This creates a memory bandwidth bottleneck, which must be
addressed at the algorithmic level.
As described in Implementing Memory Structures for Video Processing in the Vivado HLS Tool
(XAPP793) [Ref
memory architecture for achieving performance. In the context of Sobel edge detection,
proper memory architecture requires only a single access to the global memory storing the
input image and local buffer storage to create the 3 x 3 computation window. Line buffers
and other memory structures must be part of the C code given to the HLS tool in order to
generate the correct design. Implementing Memory Structures for Video Processing in the
Vivado HLS Tool provides the details on how to create line buffers and memory structures
for image and video processing. The code in the TRD has been modified to express tiered
memory architecture to meet the performance requirements of the design.

Software Architecture

This section explains the software architecture for the Zynq-7000 AP SoC ZC702 Base TRD.
Figure 2-4 illustrates a top-level view of the software architecture.
A multi-threaded Linux application is responsible for running the TRD demonstration. This
application uses the Qt-based GUI, which is displayed through Display Monitor, to obtain
user inputs. Depending on the inputs, it calls device drivers to configure the hardware and
to enable a particular data path.
The Zynq Base TRD uses PetaLinux framework for building/customizing software artifacts.
See Appendix D, PetaLinux Software Development Kit
Three major software components are involved in the Base TRD:
• Xilinx Boot Loader
• Xilinx Linux kernel
• Application
Zynq-7000 AP SoC ZC702 Base TRD
UG925 (v6.0) February 21, 2014
11], the algorithm targeted at the HLS tool must have a notion of proper
www.xilinx.com
Software Architecture
for more details on PetaLinux SDK.
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