Lcd Interface; Interfacing Lcdc With Lcd Panel - Motorola DragonBall MC68328 User Manual

values could vary among different models of LCD panels—even from the same manufac-
turer—because of different inter-pixel crosstalk characteristics.

4.1.6 LCD Interface

The LCD interface logic packs the display data in the correct size and outputs it to the LCD
panel data bus. The polarity of FRM, LP, and SCLK signals as well as pixel data can all be
programmable to suit different types of LCD panel requirements.

4.2 INTERFACING LCDC WITH LCD PANEL

LCD Data Bus (LD3-LD0)
This output bus transfers pixel data to the LCD panel for display. Depending on which
LCD panel mode was selected, data is arranged differently on the bus for each mode. Us-
ers can program the output pixel data to be negated. See the POLCF register description
for details.
First Line Marker (LFLM)
This signal indicates the start of a new display frame. The LFLM signal becomes active
after the first line pulse of the frame and remains active until the next line pulse, at which
point it de-asserts and remains inactive until the next frame. Users can program the LFLM
signal using software to be active-high or active-low. See the POLCF register description
for details.
Line Pulse (LP)
This signal latches a line of shifted data onto the LCD panel. It becomes active when a
line of pixel data is clocked into LCD panels and stays asserted for a duration of 8 pixel
clock periods. Users can program the LP signal using software to be either active-high or
active-low. See the POLCF register description for details.
MOTOROLA MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
MC68328
Figure 4-2. LCD Module Interface Signals
LACD
LFLM
LP
LCD Panel Module
LSCLK
LD0
LD1
LD2
LD3
LCD Controller
4-3