Normal Startup; Change Of Frequency; Pll Shutdown - Motorola DragonBall MC68328 User Manual

Phase-Locked Loop and Power Control
of 225 (decimal), every divisor is available to fine-tune the VCO in 32 kHz steps. The formula
for the dual-modulus divider is:
Below the value of 225, some divisors are not allowed as the P and Q relationships cannot
be met.

3.3.3 Normal Startup

When the MC68328 processor is awakened from sleep mode by a system interrupt, the PLL
achieves lock within a few milliseconds. The crystal oscillator is always on after initial pow-
erup, so the crystal startup time is not a factor. The master clock starts operation after the
PLL achieves lock.

3.3.4 Change of Frequency

To change the VCO frequency, use the sequence below. As the system clock is disabled
while the PLL loses then reacquires lock, disable all peripheral devices before making
changes to the frequency.
This fragment assumes all peripherals have been disabled and the CPU is operating at the
highest possible frequency (SYSCLK SEL = 7). FREQSEL is the address of the frequency-
select register. NEWFREQ is the new frequency value (P and Q values) to be programmed.
WAIT
WAIT1
WAIT2
* at this point, the PLL will have reacquired lock and SYSCLK will
* be stable at the new frequency and the program can continue
Normally, the master frequency will be changed only during the bootup sequence. While it
is possible to dynamically control the master frequency, it is recommended that the fre-
quency be set to its permanent value at bootup (or use the default).

3.3.5 PLL Shutdown

The procedure for PLL shut down to place the system in sleep mode is similar to changes
made to the frequency. The difference is that the system can be awakened only by an inter-
rupt or reset. While there are different approaches, the simplest is to synchronize the soft-
3-4 MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
Divisor = 14 (P + 1) + Q + 1
Where:
1 <= Q <= 14
P >= Q + 1
lea #$FFF202,A0
move.w #NEWFREQ,D1
move.w (A0),D0
bpl.w WAIT
move.w D1,(A0)
move.w (A0),D0
bmi.w WAIT1
move.w (A0),D0
bpl.w WAIT2
point to the Freq Sel Register
prepare the new frequency (Q and P)
get the contents of the register
wait for CLK32 to go high
load the new frequency
the program will wait in WAIT1
or WAIT2 during the period when the
PLL loses then reacquires lock
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