Table of Contents
Advertisement
6 SYSTEM CONTROLLER AND BUS CONTROL
6.3
Address Decoder (CE) Settings
The S1C88655 is equipped with address decoders
that can output a maximum of four chip enable
_____ _______
signals (CE0–CE3) to external devices.
_____ _______
At initial reset, the CE0–CE3 terminals are set as
output port terminals (R30–R33). For this reason,
when operating in expansion mode, the ports to be
_____
used as CE signal output terminals must be config-
ured. This setting is performed through software
which writes "1" to registers CE0–CE3 correspond-
____
ing the CE signals to be used.
However, in the MPU mode the R30 terminal is
always configured as the CE0 output port.
Table 6.3.1 shows the address range assigned to the
____
four chip enable (CE) signals.
Table 6.3.1 Address settings of CE0–CE3
Mode
CE signal
MCU
CE0
expansion
CE1
mode
CE2
CE3
MPU
CE0
expansion
mode
CE1
CE2
CE3
The arrangement of memory space for external
devices does not necessarily have to be continuous
from a subordinate address and any of the chip
enable signals can be used to assign areas in
memory. However, in the MPU mode, program
memory must be assigned to CE0.
____
The CE signals are output only when the appointed
external memory area is accessed and are not
output when internal memory is accessed.
____
Note:
The CE signals will be inactive status when
the chip enters the standby mode (HALT
mode or SLEEP mode).
38
_____
_______
_____ ______
Address
400000H–4FFFFFH
100000H–1FFFFFH
200000H–2FFFFFH
300000H–3FFFFFH
000000H–00BFFFH
010000H–0FFFFFH
100000H–1FFFFFH
200000H–2FFFFFH
300000H–3FFFFFH
_____
6.4 WAIT State Settings
In order to insure accessing of external low speed
devices during high speed operations, the S1C88655
is equipped with a WAIT function which prolongs
access time. (See the "S1C88 Core CPU Manual" for
details of the WAIT function.)
The number of wait states inserted can be selected
from a choice of eight as shown in Table 6.4.1 using
the WAIT state control register WT0–WT2.
Table 6.4.1 Setting number of WAIT states
WT2
WT1
1
1
1
1
1
0
1
0
0
1
0
1
0
0
0
0
*
The length of one state is a 1/2 clock cycle.
WAIT states set in software are inserted between
bus cycle states T3–T4.
Note, however, that WAIT states cannot be inserted
when an internal register and internal memory are
being accessed and when operating with the OSC1
oscillation circuit.
Consequently, WAIT state settings in single chip
mode are meaningless.
Figures 6.4.1 and 6.4.2 show the memory read/
write timing charts.
EPSON
WT0
Number of inserted states
1
14
0
12
1
10
0
8
1
6
0
4
1
2
0
No wait
S1C88655 TECHNICAL MANUAL
Advertisement
Table of Contents
