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4 INITIAL RESET
4.1.3 Supply voltage detection (SVD) circuit
When the SVD circuit detects that supply voltage
has dropped below level 0 four successive times
(see Chapter 7, "ELECTRICAL CHARACTERIS-
TICS"), it outputs an initial reset signal until the
supply voltage has been restored to level 2.
You can select whether or not to use the initial reset
according to the SVD circuit by mask option. If you
use it, the supply voltage must be at least level 2 for
the first sampling of the SVD circuit, when the
power is turned on. At this time, if the power
voltage level is less than level 2, the initial reset
status will not be canceled and instead the SVD
circuit will continue sampling until the supply
voltage reaches level 2 or more.
For more information, see "5.13 Supply Voltage
Detection (SVD) Circuit" in this Manual.
f
OSC1
RESET
Internal initial reset
Internal address bus
Internal data bus
Internal read signal
∗ When the initial reset by the SVD circuit with the mask option has been used, this cycle is inserted as the waiting time.
16
8192/f
[sec]
OSC1
Oscillation stable waiting time
First SVD sampling time *
Fig. 4.1.4.1 Initial reset sequence
4.1.4 Initial reset sequence
After cancellation of the LOW level input to the
RESET terminal, when the power is turned on, the
start-up of the CPU is held back until the oscillation
stabilization waiting time (8,192/f
elapsed. When the initial reset by the SVD circuit
has been used, an initial sampling time (248/f
sec.) is added as additional waiting time.
Figure 4.1.4.1 shows the operating sequence
following initial reset release.
Also, when using the initial reset by simultaneous
LOW level input into the input port, you should be
careful of the following points.
(1) During SLEEP status, since the time authoriza-
tion circuit is bypassed, an initial reset is
triggered immediately after a LOW level
simultaneous input value. In this case, the CPU
starts after waiting the oscillation stabilization
time and the SVD circuit initial sampling time
(when used with the mask option), following
cancellation of the LOW level simultaneous
input.
(2) Other than during SLEEP status, an initial reset
will be triggered 1–2 seconds after a LOW level
simultaneous input. In this case, since a reset
differential pulse (64/f
within the E0C88832/88862, the CPU will start
even if the LOW level simultaneous input status
is not canceled.
248/f
[sec]
OSC1
EPSON
sec.) has
OSC1
sec.) is generated
OSC1
PC
PC
PC
Dummy
Dummy
Dummy cycle
Reset exception processing
E0C88832/88862 TECHNICAL MANUAL
OSC1
00-0000
VECL
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