Register Descriptions: Pci Bridges; Lpc Isa Bridge (Device 20, Function 3); Programming Interface; Pci Configuration Registers - AMD SB600 Technical Reference Manual

3 Register Descriptions: PCI Bridges

3.1

LPC ISA Bridge (Device 20, Function 3)

Note: Some LPC functions are controlled by, and associated with, certain PCI configuration registers in the
SMBus/ACPI device. For more information refer to
0). The diagram below lists these LPC functions and the associated registers.
Function
3.1.1

Programming Interface

•
Write LPC_enable bit in function 0, register 64, bit 20.
•
Enable LPC address decode ranges.
•
Program DMA controller for any bus master or DMA cycles.
•
Perform LPC cycles from PCI or DMA requests from LPC agent.
3.1.2

PCI Configuration Registers

The LPC host controller supports a set of configuration register required by the PCI specification.
Registers not listed here will have this default behavior: read from the register returns 0's; write to the
register is ignored.
Subsystem ID & Subsystem Vendor ID
IO Port Decode Enable Register 1
IO Port Decode Enable Register 2
IO Port Decode Enable Register 3
IO Port Decode Enable Register 4
IO/Mem Port Decode Enable Register 5
IO/Mem Port Decode Enable Register 6
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
section 2.3: SMBus Module and ACPI Block (Device 20,
LPC
LPC Controller Enable
LPC Drive strength control
64h
Register Name
VID
DID
CMD
STATUS
Revision ID/Class Code
Cache Line Size
Latency Timer
Header Type
BIST
Base Address Reg 0
Capabilities Pointer
PCI Control
LPC Sync Timeout Count
Memory Range Register
Rom Protect 0
PCI_Reg:
C0h
--
LPC ISA Bridge (Device 20, Function 3)
Proprietary
Offset Address
00h
02h
04h
06h
08h
0Ch
0Dh
0Eh
0Fh
10h
2Ch
34h
40h
44h
45h
46h
47h
48h
49h
4Ah
4Ch
50h
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