AMD SB600 Technical Reference Manual page 242

Immediate Command Output Interface – RW – 32 bits – [Mem_Reg: Base + 60h]
Field Name
Immediate Command
Write
Immediate Command Input Interface – RW – 32 bits – [Mem_Reg: Base + 64h]
Field Name
Immediate Response
Read
Immediate Command Input Interface – RW – 16 bits – [Mem_Reg: Base + 68h]
Field Name
Immediate Command
Status
Immediate Result Valid
Reserved
Immediate Response
Result Unsolicited
Immediate Response
Result Address
Reserved
DMA Position Lower Base Address – RW – 32 bits – [Mem_Reg: Base + 70h]
Field Name
DMA Position Buffer
Enable
DMA Position Lower Base
Address Unimplemented
Bits
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Bits Default
31:0 00000000 The value written into this register is used as the verb to be
h sent out over the link when the ICB (Immediate Command
Busy) bit is set to "1". Software must ensure that the ICB bit
is cleared before writing a value into this register or
undefined behavior will result. Reads from this register will
always return 0's.
Bits Default
31:0 00000000 This register contains the value from the last response to
h come in over the link.
If multiple codecs respond in the same frame, which one of
the responses that will be saved is indeterminate.
Bits Default
0 0b
This bit is a "0" when the controller can accept an
immediate command. Software must wait for this bit to be
0 before writing a value in the ICW register.
This bit will be clear (indicating "ready") when the following
conditions are met: (1) the link is running, (2) the CORB is
not active (CORBRP = CORBWP or CORBEN is not set),
and (3) there is not an immediate command already in the
queue waiting to be sent.
Writing this bit to "1" will cause the contents of the ICW
register to be sent as a verb in the next frame. Once a
response is received the IRV bit will be set and this bit will
be cleared indicating ready to transmit another verb.
1 0b
This bit is set to a "1" by hardware when a new response is
latched into the IRR (Immediate Response Read) register.
Software must clear this bit before issuing a new command
by writing a one to it so that the software may determine
when a new response has arrived.
2 0b
Reserved. Software must use 0's for write to these bits.
3 0b
Indicates whether the response latched in the Immediate
Response Input Register is a solicited or unsolicited
response.
7:4 00h
The address of the codec which sent the response
currently latched into the Immediate Response Input.
15:8 0000h
Reserved. Software must use 0's for write to these bits.
Bits Default
0 0b When this bit is set to a "1', the controller will write the DMA
positions of each of the DMA engines to the buffer in main
memory periodically. Software can use this value to know
what data in memory is valid data.
6:1 00h Hardwired to 0. This forces 128-byte buffer alignment for
cache line fetch optimizations.
Description
Description
Description
Description
HD Audio Controllers Registers
Proprietary Page 242