AMD SB600 Technical Reference Manual page 77

Field Name
B2_B3#
BPCC_En
Data
Field Name
MSI USB
Next Item Pointer
MSI Control Out
Reserved
MSI Control
64-bit Address Capable
Reserved
Field Name
MSI Address
Field Name
MSI Data
Field Name
CAP_ID
Next Item Pointer
Offset
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
PME Data / Status – RW - 32 bits - [PCI_Reg : C4h]
Bits Default
22 1b Read only.
The state of this bit determines the action that is to occur as a
direct result of programming the function to D3
indicates that when the bridge function is programmed to
D3
23 0b Read only.
A "0" indicates that the bus power/clock control policies are
disabled. When the Bus Power/Clock Control mechanism is
disabled, the bridge's PMCSR PowerState field cannot be
used by the system software to control the power or clock of
the bridge's secondary bus.
31:24 00h Read only.
This register is used to report the state dependent data
requested by the Data_Select field. The value of this register
is scaled by the value reported by the Data_Scale field.
MSI Control – RW - 32 bits - [PCI_Reg : D0h]
Bits Default
7:0 05h
15:8 E4h
16 0b
19:17 0h
22:20 0h
23 0b
31:24 00h
MSI Address – RW - 32 bits - [PCI_Reg : D4h]
Bits Default
31:0 0h
MSI Data – RW - 16 bits - [PCI_Reg : D8h]
Bits Default
15:0 0h
DBUG_PRT Control – R - 32 bits - [PCI_Reg : E4h]
Bits Default
7:0 0Ah
15:8 00h
28:16 0E0h
Description
, its secondary bus's PCI clock will be stopped (B2).
hot
Description
MSI USB ID. Read only.
Pointer to next capability structure
Set to 1 to disable IRQ. Use MSI instead.
Reserved
MSI control field
If EHCI is in 64 bit address mode as specified by 64-bit
Addressing Capability bit in HCCPARAMS register [MEM
Reg: 08h] , this bit is set to 1 indicating that EHCI is capable
of generating a 64-bit message address. Otherwise it is set
to 0 indicating the EHCI is not capable of generating a 64-bit
address.
Read only
Reserved
Description
System-specified message address.
Description
System-specified message
Description
The value of 0Ah in this field identifies that the function
supports a Debug Port.
Pointer to next capability structure
This 12 bit field indicates the byte offset (up to 4K) within the
BAR indicated by BAR#. This offset is required to be
DWORD aligned and therefore bits 16 and 17 are always
zero.
OCHI USB 1.1 and EHCI USB 2.0 Controllers
Proprietary
.
A "1"
hot.
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