AMD SB600 Technical Reference Manual page 240

Field Name
CORB Memory error
Indication
Reserved
Field Name
CORB Size
Reserved
CORB Size Capability
RIRB Lower Base Address – RW – 32 bits – [Mem_Reg: Base + 50h]
Field Name
RIRB Lower Base
Address Unimplemented
Bits
RIRB Lower Base
Address
RIRB Upper Address – RW – 32 bits – [Mem_Reg: Base + 54h]
Field Name
RIRB Upper Base
Address
RIRB Write Pointer – RW – 16 bits – [Mem_Reg: Base + 58h]
Field Name
RIRB Write Pointer
Reserved
RIRB Write Pointer Reset
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
CORB Status – RW – 8 bits – [Mem_Reg: Base + 4Dh]
Bits Default
0 0b
7:2 00h
CORB Size – RW – 8 bits – [Mem_Reg: Base + 4Eh]
Bits Default
1:0 10b
3:2 0h
7:4 0100b
Bits Default
6:0 00h
31:7 0000000h
Bits Default
31:0 00000000
h
Bits Default
7:0 00h
14:8 00h
15 0b
Description
If this status bit is set, the controller has detected an error
in the pathway between the controller and memory. Writing
a "1" to this bit will clear the bit, but a CRST must be
performed before operation continues/
Reserved. Software must use 0's for write to these bits.
Description
These bits have no functional impact to the hardware.
This HD Audio controller only supports 256 entries.
Reserved. Software must do a read-modify-write to
preserve the value of these bits.
Hardwired to 0100b indicating this controller only supports
a CORB size of 256 entries.
Description
Hardwired to 0. This forces 128-byte buffer alignment for
cache line fetch optimizations.
Upper 25 bits of the 32 bits Lower Base Address of the
Response Input Ring Buffer, allowing the RIRB Base
Address to be assigned on any 2 KB boundary. This
register must not be written when the DMA engine is
running or the DMA transfer may be corrupted.
Description
Upper 32 bits address of the RIRB. This register must not
be written when the DMA engine is running or the DMA
transfer may be corrupted.
Description
This field indicates the last valid RIRB entry written by the
DMA controller. Software reads this field to determine how
many responses it can read from the RIRB. The value read
indicates the RIRB Write Pointer offset in two dwords since
each RIRB entry is two dwords. This field may be read
while the DMA engine is running.
Reserved. Software must do a read-modify-write to
preserve the value of these bits.
Software writes a "1" to this bit to reset the RIRB Write
Pointer to 0's. The DMA engine must be stopped prior to
resetting the Write Pointer or else DMA transfer may be
corrupted. This bit will always be read as 0.
Proprietary
HD Audio Controllers Registers
Page 240