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Bus-master IDE Status - RW- 8 bits - [IO_Reg: BAR4 + 02/0Ah]
Field Name
Bus Master Active
Bus Master DMA Error
IDE Interrupt
Reserved
Master Device DMA
Capable
Slave Device DMA
Capable
Simplex Only
Descriptor Table Pointer - RW- 32 bits - [IO_Reg: BAR4 + 04/0Ch]
Field Name
Reserved
Descriptor Table Base
Address
2.1.4
BAR5 Registers
These are the AHCI memory map registers. The base address is defined through the ABAR (BAR5) register.
Vendor Specific registers
Port 0 port control registers
Port 1 port control registers
Port 2 port control registers
Port 3 port control registers
2.1.4.1
Generic Host Control
The following registers apply to the entire HBA.
Register Name
Host Capabilities(CAP)
Global Host Control(GHC)
Interrupt Status(IS)
Ports Implemented(PI)
Version(VS)
Command Completion Coalescing Control(CCC_CTL)
Command Completion Coalescing Ports(CCC_PORTS)
Enclosure Management Location(EM_LOC)
Enclosure Management Control(EM_CTL)
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Bits
Default
0
0b
Bus Master IDE active. This bit is set to 1 when bit 0 in the Bus
Master IDE command address register is set to 1. The IDE host
controller sets this bit to 0 when the last transfer for a region is
performed. This bit is also set to 0 when bit 0 of the Bus Master
IDE command register is set to 0.
1
0b
IDE DMA error. This bit is set when the IDE host controller
encounters a target abort, master abort, or Parity error while
transferring data on the PCI bus. Write '1' clears this bit
2
0b
IDE Interrupt. Indicates when an IDE device has asserted its
interrupt line. IRQ14 is used for the Primary channel and IRQ15 is
used for the secondary channel. If the interrupt status bit is set to
0, by writing a 1 to this bit while the interrupt line is still at the
active level, this bit remains 0 until another assertion edge is
detected on the interrupt line.
4:3
Reserved.
5
0b
Device 0 (Master) DMA capable.
6
0b
Device 1 (Slave) DMA capable.
7
0b
Read Only
Simplex only. This bit is hard-wired as 0.
Bits
Default
1:0
0h
31:2
0000_0000h
Register Name
Generic Host Control
Reserved
Description
Description
Reserved. Always read as 0's.
Base Address of Descriptor Table. These bits correspond to
Address [31-02].
Offset Address
00h-03h
04h-07h
08h-0Bh
0Ch-0Fh
10h-13h
14h-17h
18h-1Bh
1Ch-1Fh
20h-23h
SATA Registers (Device 18, Function 0)
Proprietary
Offset Address
00h-23h
24h-9Fh
A0h-FFh
100h-17Fh
180h-1FFh
200h-27Fh
280h-2FFh
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