AMD SB600 Technical Reference Manual page 102

Field Name
Interrupt Line
Interrupt Line register
Field Name
Interrupt Pin
Interrupt Pin register
Field Name
Min_Gnt
Min_Gnt register
Field Name
Max_Lat
Max_Lat register
Field Name
Reserved
KB2RstEnable
Reserved
PCI Control register
Field Name
Reserved
ExtraROM AddrEnable2
Reserved
WatchDogDecodeEn
ExtraROM AddrEnable1
MiscfuncEnable
Reserved
MiscFunction register
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Interrupt Line - R - 8 bits - [PCI_Reg: 3Ch]
Bits Default
7:0 00h This module does not generate interrupt. This register is
hardcoded to 0.
Interrupt Pin – R - 8 bits - [PCI_Reg: 3Dh]
Bits Default
7:0 00h This register specifies which interrupt pin the device issues.
This module does not generate interrupt but contains the
actual interrupt controller. This register is hardcoded to 0.
Min_Gnt - R - 8 bits - [PCI_Reg: 3Eh]
Bits Default
7:0 00h This register specifies the desired settings for Latency Timer
values. Value of 0 indicates that the device has no major
requirements for the setting. This value is hardcoded to 0.
Max_Lat - R - 8 bits - [PCI_Reg: 3Fh]
Bits Default
7:0 00h This register specifies the desired settings for Latency Timer
values. Value of 0 indicates that the device has no major
requirements for the setting. This value is hardcoded to 0.
PCI Control- RW - 8 bits - [PCI_Reg: 40h]
Bits Default
1:0 00b
2 0b When set, KeyBoard reset (KBRST#) pin will generate a
system wide reset (ARST#) for P4 system; for K8 system,
additional control by PMIO 66h Bit 5 determines whether INIT#
or ARST# is generated
7:3 0h
MiscFunction- RW - 8 bits - [PCI_Reg: 41h]
Bits Default
0 0b
1 0b This bit only has meaning if xbus ROM is used. If this bit is
set, addresses between FFF80000h to FFFDFFFFh will be
directed to the ROM interface
2 0b
3 0b Enables watchdog decode
4 0b This bit is meaningful if ROM interface is strapped to the xbus
ROM (sits on PCI bus). If this bit is set, addresses between
0E0000h to 0EFFFFh will be directed to the ROM interface.
5 0b When set, this module will decode cycles to IO C50, C51, C52:
GPM controls.
7:6 00b
Description
Description
Description
Description
Description
Description
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary Page 102