AMD SB600 Technical Reference Manual page 294

Field Name
Update Ended Interrupt Flag(UF)
Alarm Interrupt Flag (AF)
Periodic Interrupt Flag (PF)
Interrupt Request Flag (IRQF)
Register C: Control register
Field Name
DateAlarm
Scratchbit
VRT
Date Alarm Register
Field Name
AltCentury
AltCentury Register
Field Name
Century
Century Register
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Register C - R – 8 bits - [RTC_Reg: 0Ch]
Bits Default
4 0b
5 0b
6 0b
7 0b
DateAlarm - RW – 8 bits - [RTC_Reg: 0Dh]
Bits Default
5:0 00h DateAlarm in BCD format and is considered when it is
set to non-zero value. If this value is set to 0, then date
is not compared for alarm generation.
6 0b
7 1b Valid RAM and Time; refer to VRT_T1 and VRT_T2
registers (PMIO 3E/3F)
AltCentury - RW – 8 bits - [RTC_Reg: 32h]
Bits Default
7:0 00h (This register is accessed only when DV0=0 and
PM_Reg 7Ch Bit4=1.) Binary-Code-Decimal format.
Leap year correction is done through hardware. This
register can be set by software (SET bit of Register B =
1) or can be automatically updated by hardware every
century. When set by software, hardware updating is
disabled.
Century - RW – 8 bits - [RTC_Reg: 48h]
Bits Default
7:0 00h (This register is accessed only when DV0=1) Binary-
Code-Decimal format. Leap year correction is done
through hardware. This register can be set by software
(SET bit of Register B = 1) or can be automatically
updated by hardware every century. When set by
software, hardware updating is disabled.
Description
This bit is set to one after each update cycle.
Reading Register C clears UF.
This bit is set to one if second, minute and hour time
has matched the second, minute and hour alarm
time. Reading Register C clears AF bit.
This bit is set to one when an edge is detected on
the selected tap (through RS3 to RS0) of the
frequency divider. Reading Register C clears PF bit.
Logically, IRQF =
(PF*PIE)+(AF*AIE)+(UF*UIE)+(WF*WIE) where WF
and WIE are defined in Extended Control Register
4A and 4B. Reading Register C clears IRQF bit.
Any time the IRQF bit is set to one, the #IRQ pin is
driven low.
Description
Description
Description
Proprietary
Real Time Clock (RTC)
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