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Pin Name
Multi-function
(Note 1)
Selection
GPIO4/
SMBus Reg5Eh[Bit 7]
SMARTVOLT/
0: GPIO if not used by
SATA
SATA_IS2#
1: SMARTVOLT
GPIO5/
SMBus Reg9Ah[Bit7]
SHUTDOWN#/
1 – SMARTVOLT2
SMARTVOLT2
0 – use
PMIO_59h[Bit5] to set
function
PM IO Reg59h[Bit 5]
0: GPIO
1: SHUTDOWN#
GPIO6/
PM IO Reg60h[Bit 7]
GHI#/
0: GHI#
SATA_IS1#
1: GPIO if not used by
SATA
GPIO7/
Strap on PCI AD [23]
WD_PWRGD
0: GPIO
1: WD_PWRGD
GPIO8/
Input/Output pin only
DDC1_SDA
GPIO9/
Input/Output pin only
DDC1_SCL
GPIO10/
GPIO if not used by
SATA_IS0#
SATA
GPIO11/
SMBus RegABh[Bit 6]
0: SPI_DO
SPI_DO
1: GPIO
GPIO12/
SMBus RegABh[Bit 7]
0: SPI_DI
SPI_DI
1: GPIO
GPIO13/
SMBus Reg83h[Bit 4]
0: LAN_RST#
LAN_RST#
1: GPIO
GPIO14/
SMBus Reg83h[Bit 5]
0: ROM_RST#
ROM_RST#
1: GPIO
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Output Enable
Input if GPI
(On SMBus
(On SMBus
Controller)
Controller)
Bus 00h/ Dev14h/
Bus 00h/
Fun00
Dev14h/ Fun00
RegA9h[Bit 0]
RegAAh[Bit 0]
0: Output
*Note 3
1: Input (Tri-state)
*Note 2
SMBus Reg9Ah[7]=0
RegAAh[Bit 1]
RegA9h[Bit 1]
*Note 3
0: Output
1: Input (Tri-state)
*Note 2
RegA9h[Bit 2]
RegAAh[Bit 2]
*Note 3
0: Output
1: Input (Tri-state)
*Note 2
RegA9h[Bit 3]
RegAAh[Bit 3]
0: Output
*Note 3
1: Input (Tri-state)
*Note 2
Reg A9h[Bit 4]
Reg AAh[Bit 4]
*Note 3
0: Output
1: Input (Tri-state)
*Note 2
Reg A9h[Bit 5]
Reg AAh[Bit 5]
0: Output
*Note 3
1: Input (Tri-state)
*Note 2
Reg ABh[Bit 1]
Reg ABh[Bit 2]
0: Output
1: Input (Tri-state)
Reg A9h[Bit 6]
Reg AAh[Bit 6]
0: Output
*Note 3
1: Input (Tri-state)
*Note 2
Reg A9h[Bit 7]
Reg AAh[Bit 7]
0: Output
*Note 3
1: Input (Tri-state)
*Note 2
Reg 82h[Bit 4]
Reg 83h[Bit 0]
0: Output
1: Input (Tri-state)
Reg 82h[Bit 5]
Reg 83h[Bit 1]
0: Output
1: Input (Tri-state)
Proprietary
Output if GPO
Power
(On SMBus
Domain
Controller)
Bus 00h/
Dev14h/ Fun00
RegA8h[Bit 0]
S0
RegA8h[Bit 1]
S0
RegA8h[Bit 2]
S0
RegA8h[Bit 3]
S0
Reg A8h[Bit 4]
S0
Reg A8h[Bit 5]
S0
Reg ABh[Bit 0]
S0
Reg A8h[Bit 6]
S0
Reg A8h[Bit 7]
S0
Reg 82h[Bit 0]
S0
Reg 82h[Bit 1]
S0
GPIO/GPOC
Page 278
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