AMD Geode SC2200 Data Book
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AMD Geode SC2200 Data Book

AMD Geode SC2200 Data Book

Processor
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AMD Geode™ SC2200 Processor
Data Book
March 2006
Publication ID: 32580B
AMD Geode™ SC2200 Processor Data Book

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Summary of Contents for AMD Geode SC2200

  • Page 1 AMD Geode™ SC2200 Processor Data Book March 2006 Publication ID: 32580B AMD Geode™ SC2200 Processor Data Book...
  • Page 2 Contacts www.amd.com Trademarks AMD, the AMD Arrow logo, and combinations thereof, and Geode and Virtual System Architecture are trademarks of Advanced Micro Devices, Inc. Microsoft and Windows are registered trademarks of Microsoft Corporation in the United States and/or other jurisdictions.

  • Page 3: Table Of Contents

    Legacy Functional Blocks ........... . 136 AMD Geode™ SC2200 Processor Data Book...
  • Page 4 Data Book Revision History ..........448 Contents AMD Geode™ SC2200 Processor Data Book...

  • Page 5: List Of Figures

    VIP Block Diagram ............323 AMD Geode™ SC2200 Processor Data Book...
  • Page 6 Enhanced Parallel Port Timing Diagram ........430 List of Figures AMD Geode™ SC2200 Processor Data Book...
  • Page 7 BGU481 Package - Bottom View ..........446 AMD Geode™ SC2200 Processor Data Book...

  • Page 8: List Of Figures

    32580B List of Figures AMD Geode™ SC2200 Processor Data Book...

  • Page 9: List Of Tables

    Banks 0 and 1 - Common Control and Status Register Map ......124 AMD Geode™ SC2200 Processor Data Book...
  • Page 10 F2: PCI Header Registers for IDE Controller Support Summary ..... 190 List of Tables AMD Geode™ SC2200 Processor Data Book...
  • Page 11 Ball Capacitance and Inductance ..........374 AMD Geode™ SC2200 Processor Data Book...
  • Page 12 Edits to Current Revision ........... 449 List of Tables AMD Geode™ SC2200 Processor Data Book...

  • Page 13: 1.0Overview

    Overview General Description The AMD Geode™ SC2200 processor is a member of the AMD Geode processor family of fully integrated x86 system chips. The SC2200 processor includes: • The Geode GX1 processor module combines advanced CPU performance with MMX™ support, fully acceler-...

  • Page 14: Features

    — Sx state control of three power planes — Cx/Sx state control of clocks and PLLs — Thermal event input — Wakeup event support: – Three general-purpose events – AC97 codec event – UART2 RI# signal – Infrared (IR) event AMD Geode™ SC2200 Processor Data Book Overview...
  • Page 15 Serial Port (UART): — UART1, 16550A compatible (SIN, SOUT, BOUT pins), used for SmartCard interface — UART2, 16550A compatible — Enhanced UART with fast Infrared (IR) AMD Geode™ SC2200 Processor Data Book 32580B Other Features ■ High-Resolution Timer: — 32-Bit counter with 1 μs count interval ■...
  • Page 16 32580B Overview AMD Geode™ SC2200 Processor Data Book...

  • Page 17: 2.0Architecture Overview

    The GX1 processor (silicon revision 8.1.1) is the central module of the SC2200. For detailed information regarding the GX1 module, refer to the AMD Geode™ GX1 Proces- sor Data Book and the AMD Geode™ GX1 Processor Sili- con Revision 8.1.1 Specification Update document.

  • Page 18: Table 2-1. Sc2200 Memory Controller Register Summary

    MC_DR_ACC. Memory Controller Dirty RAM Access Register MC_MEM_CNTRL1 (R/W) 100: ÷ 3.5 101: ÷ 4 110: ÷ 4.5 111: ÷ 5 Architecture Overview Reset Value 248C0040h 00000801h 41104110h 2A733225h 00000000h 00000000h 0000000xh Reset Value: 248C0040h AMD Geode™ SC2200 Processor Data Book...
  • Page 19 1: 2 Core clocks. FSTRDMSK (Fast Read Mask). Do not allow core reads to bypass the request FIFO. 0: Disable. 1: Enable. AMD Geode™ SC2200 Processor Data Book MC_MEM_CNTRL2 (R/W) 100: Shift 2 core clocks 101: Shift 2.5 core clocks...
  • Page 20 1111: 16 CLK 100: 4 CLK 110: 6 CLK 101: 5 CLK 111: 7 CLK 100: 4 CLK 110: 6 CLK 101: 5 CLK 111: 7 CLK AMD Geode™ SC2200 Processor Data Book Architecture Overview Reset Value: 41104110h Reset Value: 2A733225h...
  • Page 21 31:2 RSVD (Reserved). Write as 0. D (Dirty Bit). This bit is read/write accessible. V (Valid Bit). This bit is read/write accessible. AMD Geode™ SC2200 Processor Data Book 100: 4 CLK 110: 6 CLK 101: 5 CLK 111: 7 CLK...

  • Page 22: Video Processor Module

    8-bit bus, at the Video Processor. For more information about the GX1 module’s interface to the Video Processor, see the “Display Controller” chapter in the AMD Geode™ GX1 Processor Data Book. Video Processor Module The Video Processor provides high resolution and graphics for a CRT or TFT/DSTN interface.

  • Page 23: Core Logic Module

    Signals" on page 57, Section 3.4.13 "Fast Infrared (IR) Port Interface Signals" on page 67, and Section 3.4.12 "Parallel Port Interface Signals" on page 66. AMD Geode™ SC2200 Processor Data Book 32580B The Core Logic module interface to the GX1 module con- sists of seven miscellaneous connections, the PCI bus interface signals, plus the display controller connections.

  • Page 24: Clock, Timers, And Reset Logic

    • Power-on, as indicated by POR# signal assertion. • A WATCHDOG reset event (see Section 4.3.2 "WATCHDOG Registers" on page 84). • Software initiated system reset. AMD Geode™ SC2200 Processor Data Book Architecture Overview...

  • Page 25: 3.0Signal Definitions

    Straps are not the default signal, shown with system signals for reader convenience. However, they are also listed with the appropriate functional group. AMD Geode™ SC2200 Processor Data Book 3.0Signal Definitions separated by a plus sign (+). A slash (/) in a signal name means that the function is always enabled and available (i.e., cycle multiplexed).
  • Page 26 GNT1#+DID1 A[23:0]/AD[23:0] D[7:0]/AD[31:24] D[11:8]/C/BE[3:0]# Sub-ISA/PCI Bus D12/PAR Interface D13/TRDY# D14/IRDY# D15/STOP# BHE#/DEVSEL# ROMCS#/BOOT16 RD#+CLKSEL0 GPIO0+TRDE# GPIO32+LAD0 GPIO33+LAD1 GPIO34+LAD2 GPIO/LPC Bus GPIO35+LAD3 Interface GPIO36+LDRQ# GPIO39+SERIRQ TEST1+PLL6B TEST0+PLL2B Test and Measurement TEST2+PLL5B Interface GTEST TDP, TDN AMD Geode™ SC2200 Processor Data Book...

  • Page 27: Strap Options

    Pin Multiplexing Register (PMR). See Section 4.2 "Multiplexing, Interrupt Selection, and Base Address Registers" on page 76 for a detailed description of this register. AMD Geode™ SC2200 Processor Data Book 32580B Table 3-1. Signal Definitions Legend Mnemonic...

  • Page 28: Figure 3-2. Bgu481 Ball Assignment Diagram

    MD28 MD50 MD49 MD54 MD53 MD21 DQM6 DQM2 MD55 MA8 DQM1 MD13 MA11 CS1# MD18 MD48 MD20 MD51 MD11 SDCKI MD19 MD22 MD17 MA5 MD15 MD14 MD12 SDCKO MD16 MD8 MD10 MD9 MA12 MD23 AMD Geode™ SC2200 Processor Data Book...

  • Page 29: Table 3-2. Bgu481 Ball Assignment - Sorted By Ball Number

    HSYNC CCCRT GREEN WIRE BLUE WIRE PLL2 6, 2 14/14 TFTD13 F_AD7 14/14 AMD Geode™ SC2200 Processor Data Book Power Ball Rail Configuration Signal Name 6, 2 Cycle Multiplexed TFTD1 F_AD6 Strap (See Table 6, 2 3-4 on page 45.)
  • Page 30 3-4 on page 45.) PMR[9] = 0 and PMR[4] = 0 22.5 PMR[9] = 0 and PMR[4] = 1 22.5 PMR[9] = 1 and PMR[4] = 1 22.5 PMR[6] = 0 PMR[6] = 1 AMD Geode™ SC2200 Processor Data Book...
  • Page 31 F_AD0 14/14 INTB# 22.5 SSUSB GPIO9 22.5 DCD2# 22.5 IDE_IOW1# 22.5 SDTEST2 22.5 AMD Geode™ SC2200 Processor Data Book Power Ball Rail Configuration Signal Name GPIO7 PMR[23] = 0 and (PMR[27] = 0 and FPCI_MON = 0) RTS2# PMR[23] = 1 and...
  • Page 32 Cycle Multiplexed Cycle Multiplexed 22.5 PMR[28] = 0 PMR[28] = 1 22.5 22.5 Cycle Multiplexed 22.5 22.5 Cycle Multiplexed 22.5 22.5 Cycle Multiplexed 22.5 22.5 Cycle Multiplexed 22.5 22.5 22.5 Cycle Multiplexed 22.5 22.5 AMD Geode™ SC2200 Processor Data Book...
  • Page 33 AD13 C/BE1# 22.5 22.5 AD15 22.5 22.5 VPD2 VPD1 VPD0 GPIO39 22.5 SERIRQ AD11 AD14 AMD Geode™ SC2200 Processor Data Book Power Ball Rail Configuration Signal Name GPIO38/IRRX2 Cycle Multiplexed LPCPD# GPIO37 LFRAME# Cycle Multiplexed C/BE0# Cycle Multiplexed Cycle Multiplexed...
  • Page 34 PMR[24] = 1 Signal Definitions Buffer Power (PU/PD) Type Rail Configuration Cycle Multiplexed AC97 Strap (See Table STRP 3-4 on page 45.) AC97 Strap (See Table STRP 3-4 on page 45.) PMR[25] = 1 AMD Geode™ SC2200 Processor Data Book...
  • Page 35 IDE_DATA15 TFTD7 IDE_DATA14 TFTD17 IDE_DATA13 TFTD15 CORE CORE CORE CORE SDCLK3 GXCLK FP_VDD_ON TEST3 AMD Geode™ SC2200 Processor Data Book Power Ball Rail Configuration Signal Name GPIO16 PC_BEEP Cycle Multiplexed F_DEVSEL# PMR[24] = 0 PMR[24] = 1 Cycle Multiplexed IDE_DATA12...
  • Page 36 , TS PMR[16] = 0 22.5 PMR[16] =1 22.5 WIRE PMR[29] = 1 PMR[29] = 0 , TS , TS WIRE PMR[29] = 1 , TS PMR[29] = 0 2/14 , TS , TS AMD Geode™ SC2200 Processor Data Book...
  • Page 37 MD47 , TS AJ18 MD45 , TS AJ19 MD42 , TS AJ20 AJ21 SDCLK0 AJ22 AJ23 AJ24 AJ25 AMD Geode™ SC2200 Processor Data Book Power Ball Rail Configuration Signal Name MD11 AJ26 AJ27 SDCLK_IN MD19 AJ28 AJ29 MD22 AJ30 MD17...
  • Page 38 Is back-drive protected (MD[63:0], DPOS_PORT1, DNEG_PORT1, DPOS_PORT2, DNEG_PORT2, DPOS_PORT3, DNEG_PORT3, ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#, PD[7:0], PE, SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#, PWRCNT[2:1]). Signal Definitions Buffer Power (PU/PD) Type Rail Configuration , TS , TS , TS , TS AMD Geode™ SC2200 Processor Data Book...

  • Page 39: Table 3-3. Bgu481 Ball Assignment - Sorted Alphabetically By Signal Name

    Ball No. AB1C AB1D AB2C AB2D AC97_CLK AC97_RST# ACK# AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AMD Geode™ SC2200 Processor Data Book Signal Name Ball No. AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30...
  • Page 40 INTC# INTD# INTR_O IOCHRDY IOCS0# IOCS1# IOCS1# IOR# IOW# IRDY# IRQ9 IRQ14 IRQ15 IRRX1 IRTX LAD0 AMD Geode™ SC2200 Processor Data Book Signal Definitions Signal Name Ball No. LAD1 LAD2 LAD3 LDRQ# LED# LFRAME# LOCK# LPC_ROM LPCPD# AL14 AH15 AK15...
  • Page 41 AA31 NC (Total of 8) A23, A24, A25, B23, B26, C23, C24, D24 ONCTL# OVER_CUR# PC_BEEP PCICLK PCICLK0 PCICLK1 PCIRST# AMD Geode™ SC2200 Processor Data Book Signal Name Ball No. PERR# PLL2B PLL5B PLL6B POR# POWER_EN PWRBTN# PWRCNT1 PWRCNT2 RASA#...
  • Page 42 W16, W17, W30, AB2, AB30, AE2, AE4, AE28, AE30, AH7, AH13, AH19, AH25, AK2, AK7, AK10, AK22, AK25, AK30, AL1, AL13, AL16, AL19, AL31 SSCRT VSYNC WEA# AH12 X27I X27O X32I X32O AMD Geode™ SC2200 Processor Data Book Signal Definitions...

  • Page 43: Strap Options

    GNT1# Note: Accuracy of internal PU/PD resistors: 80K to 250K. Location of the GCB (General Configuration Block) cannot be determined by software. See the AMD Geode™ SC2200 Proces- sor Specification Update document. AMD Geode™ SC2200 Processor Data Book of 1.5 KΩ be placed on the balls listed in Table 3-4. The value of the resistor is important to ensure that the proper state is read during the power-up sequence.

  • Page 44: Multiplexing Configuration

    TFTD13 TFTD15 TFTD17 TFTD7 TFTD10 TFTD11 TFTD8 TFTD9 TFTD5 TFTDE TFTD0 TFTDCK TFTD1 PMR[12] = 0 GPIO0 Signal Definitions Alternate Signal Configuration TFT, CRT, PCI, GPIO, System PMR[24] = 1 GPIO PMR[12] = 1 AMD Geode™ SC2200 Processor Data Book...
  • Page 45 GPIO35 GPIO36 GPIO37 GPIO38/IRRX2 GPIO39 SIN2 AC97_RST# SDATA_IN BIT_CLK Internal Test PLL6B PLL5B PLL2B AMD Geode™ SC2200 Processor Data Book Configuration GPIO PMR[19] = 0 AB2C AB2D GPIO PMR[16] = 0 DTR1#/BOUT1 PMR[6] = 0 SOUT3 SIN3 GPIO PMR[14] = 0 and PMR[22] =...

  • Page 46: Table 3-6. Three-Signal/Group Multiplexing

    PMR[7] = 0 GPIO1 PMR[23] = 1 and PMR[13] = 0 UART2 RI2# PMR[18] = 1 and PMR[8] = 0 AMD Geode™ SC2200 Processor Data Book Signal Definitions Alternate2 Signal Configuration GPIO GPIO14 PMR[21] = 1 and PMR[2] = 1...

  • Page 47: Table 3-7. Four-Signal/Group Multiplexing

    CTS2# PMR[8] = 0 D28 GPIO6 PMR[18] = 0 DTR2#/BOUT2 C28 GPIO9 DCD2# PMR[8] = 0 B29 GPIO10 DSR2# AMD Geode™ SC2200 Processor Data Book Alternate1 Signal Configuration Internal Test TEST3 PMR[23] = 0 and PMR[29] = 1 Alternate1 Alternate2...

  • Page 48: Signal Descriptions

    Power On Reset. POR# is the system reset signal gen- erated from the power supply to indicate that the system should be reset. Signal Definitions SOUT1 SYNC SOUT2 ROMCS# PCICLK1 SDATA_OUT PCICLK0 GNT1# GNT0# AMD Geode™ SC2200 Processor Data Book...
  • Page 49 X27I X27O CLK27M PCIRST# AMD Geode™ SC2200 Processor Data Book Description Crystal Connections. Connected directly to a 32.768 KHz crystal. This clock input is required even if the inter- nal RTC is not being used. Some of the internal clocks are derived from this clock.

  • Page 50: Memory Interface Signals

    SDRAM Clocks. SDRAM uses these clocks to sample all control, address, and data lines. To ensure that the Suspend mode functions correctly, SDCLK3 and SDCLK1 should be used with CS1#. SDCLK2 and SDCLK0 should be used together with CS0#. Signal Definitions AMD Geode™ SC2200 Processor Data Book...
  • Page 51 VPD3 VPD2 VPD1 VPD0 VPCKIN AMD Geode™ SC2200 Processor Data Book Description SDRAM Clock Input. The SC2200 samples the memory read data on this clock. Works in conjunction with the SDCLK_OUT signal. SDRAM Clock Output. This output is routed back to SDCLK_IN.
  • Page 52 GPIO17+ IOCS0# IDE_CS1# ACK#+FPCICLK IDE_DATA4 GXCLK+TEST3 The TFT interface is muxed with the IDE interface or the Par- allel Port. See Table 3-5 on page 46 and Table 3-6 on page 48 for details. GPIO20+DOCCS# AMD Geode™ SC2200 Processor Data Book...

  • Page 53: Pci Bus Interface Signals

    C/BE2# C/BE1# C/BE0# INTA# INTB# INTC# INTD# AMD Geode™ SC2200 Processor Data Book Description ACCESS.bus 1 Serial Data. This is the bidirectional serial data signal for the interface. Note: If AB1D function is selected but not used, tie AB1D high.
  • Page 54 AD[31:0]. During a write, it indicates that the target is prepared to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. This signal is internally connected to a pull-up resistor. Signal Definitions AMD Geode™ SC2200 Processor Data Book...
  • Page 55 Type STOP# LOCK# DEVSEL# AMD Geode™ SC2200 Processor Data Book Description Target Stop. STOP# is asserted to indicate that the cur- rent target is requesting that the master stop the current transaction. This signal is used with DEVSEL# to indicate retry, disconnect, or target abort.
  • Page 56 Each of these signals is internally connected to a pull-up resistor. GNT0# must have a pull-up resistor of 1.5 KΩ and GNT1# must have a pull-down resistor of 1.5 KΩ. Signal Definitions DID1 (Strap) DID0 (Strap) AMD Geode™ SC2200 Processor Data Book...
  • Page 57 TRDE# IOR# IOW# DOCR# DOCW# IRQ9 IOCHRDY AMD Geode™ SC2200 Processor Data Book Description Address Lines Data Bus Byte High Enable. With A0, defines byte accessed for 16 bit wide bus cycles. I/O Chip Selects ROM or Flash ROM Chip Select DiskOnChip or NAND Flash Chip Select Transceiver Data Enable Control.
  • Page 58 IRQ level is delivered during a designated time slot. Note: If SERIRQ function is selected but not used, tie SERIRQ high. Signal Definitions GPIO35 GPIO34 GPIO33 GPIO32 GPIO36 GPIO37 GPIO38/IRRX2 GPIO39 AMD Geode™ SC2200 Processor Data Book...

  • Page 59: Table 6-44. Dma

    IDE_DREQ1 IDE_DACK0# IDE_DACK1# IRQ14 IRQ15 AMD Geode™ SC2200 Processor Data Book Description IDE Reset. This signal resets all the devices that are attached to the IDE interface. IDE Address Bits. These address bits are used to access a register or data port in a device on the IDE bus.
  • Page 60 (i.e., bit 7 of the EXCR1 Register is set). Signal Definitions SDTEST3 IRRX1 CLKSEL1 (Strap) CLKSEL2 (Strap) IRTX GPIO7+ IDE_DACK1# GPIO8+ IDE_DREQ1 GPIO18 GPIO6+IDE_IOR1# AMD Geode™ SC2200 Processor Data Book...
  • Page 61 Ball No. Type RI2# DCD2# DSR2# AMD Geode™ SC2200 Processor Data Book Description Ring Indicator. When low, indicates to the modem that a telephone ring signal has been received by the modem. They are monitored during power-off for wakeup event detection.
  • Page 62 When the cycle is aborted, ASTRB# becomes inactive (high). Signal Definitions TFTDE+FPCICLK TFTD2+INTR_O TFTD3+F_C/BE1# TFTD4+F_C/BE0# TFTD5+SMI_O TFTD13+F_AD7 TFTD1+F_AD6 TFTD11+F_AD5 TFTD10+F_AD4 TFTD9+F_AD3 TFTD8+F_AD2 TFTD7+F_AD1 TFTD6+F_AD0 TFTD14+F_C/BE2# TFTD15+F_C/BE3# TFTD16+ F_IRDY# AMD Geode™ SC2200 Processor Data Book...
  • Page 63 Type IRRX1 IRRX2/GPIO38 IRTX AMD Geode™ SC2200 Processor Data Book Description Data Strobe. When low, indicates to the printer that valid data is available at the printer port. This signal is in TRI- STATE after a 0 is loaded into the corresponding control register bit.

  • Page 64: Power Management Interface Signals

    On / Off Control. This signal indicates to the main power supply that power should be turned on. This signal is an open-drain output. Signal Definitions F_TRDY# TFT_PRSNT (Strap) F_GNT0# CLKSEL3 (Strap) F_STOP# . If wakeup from GPIO16+ F_DEVSEL# AMD Geode™ SC2200 Processor Data Book...
  • Page 65 Type PWRBTN# PWRCNT1 PWRCNT2 THRM# AMD Geode™ SC2200 Processor Data Book Description Power Button. Input used by the power management logic to monitor external system events, most typically a system on/off button or switch. The signal has an internal pull-up of 100 KΩ, a Schmitt-...

  • Page 66: Gpio Interface Signals

    AB1D+IOCS1# DTR2#/BOUT2+ IDE_IOR1#+ SDTEST5 RTS2#+IDE_DACK1# +SDTEST0 CTS2#+IDE_DREQ1 +SDTEST4 DCD2#+IDE_IOW1#+ SDTEST2 DSR2#+IDE_IORDY1 +SDTEST1 RI2#+IRQ15 AB2C AB2D IOR#+DOCR# IOW#+DOCW# PC_BEEP+ F_DEVSEL# IOCS0#+TFTDCK DTR1#/BOUT1 INTC#+IOCHRDY DOCCS#+TFTD0 AB1C+DOCCS# LAD0 LAD1 LAD2 LAD3 LDRQ# LFRAME# LPCPD# SERIRQ IDE_DATA8 IDE_DATA11 AMD Geode™ SC2200 Processor Data Book...

  • Page 67: Jtag Interface Signals

    JTAG Interface Signals Signal Name Ball No. Type AMD Geode™ SC2200 Processor Data Book Description Fast-PCI Bus Monitoring Signals. When enabled, this group of signals provides for monitoring of the internal Fast-PCI bus for debug purposes. To enable, pull up FPCI_MON (ball A4).
  • Page 68 For normal operation leave unconnected. Type Description PLL2 Analog Ground Connection. Signal Definitions FP_VDD_ON+ TEST3 FP_VDD_ON+ GXCLK PLL5B PLL6B PLL2B TEST1 TEST2 TEST0 GPIO6+ DTR2#/BOUT2+ IDE_IOR1# GPIO8+CTS2#+ IDE_DREQ1 SIN2 GPIO9+DCD2#+ IDE_IOW1# GPIO10+DSR2#+ID E_IORDY1 GPIO7+RTS2#+ IDE_DACK1# AMD Geode™ SC2200 Processor Data Book...
  • Page 69 See Table 3-3 on page 41. (Total of 8) must be connected, even if the function is not used. All power sources except V AMD Geode™ SC2200 Processor Data Book (Continued) Type Description PLL3 Analog Ground Connection. 3.3V PLL2 Analog Power Connection. Low noise power for PLL2 and PLL5.
  • Page 70 32580B Signal Definitions AMD Geode™ SC2200 Processor Data Book...

  • Page 71: 4.0General Configuration Block

    General Configuration block registers. All subsequent writes to this address, are ignored until system reset. Note: Location of the General Configuration Block can- not be determined by software. See the AMD Geode™ SC2200 Processor Specification Update document. Reserved bits in the General Configuration block should be read as written unless otherwise specified.

  • Page 72: Multiplexing, Interrupt Selection, And Base Address Registers

    See PMR[23] See PMR[23] See PMR[23] See PMR[23] See PMR[23] See PMR[23] See PMR[23] See PMR[23] See PMR[23] See PMR[23] FPCI_MON = 1 and see PMR[0] FPCI_MON = 1 FPCI_MON = 1 FPCI_MON = 1 AMD Geode™ SC2200 Processor Data Book...
  • Page 73 C24 / AC4 IDE_DREQ0 C25 / AD4 IDE_DACK0# A22 / AA1 IDE_RST# A25 / AD1 IDE_IORDY0 D25 / AF1 IRQ14 AMD Geode™ SC2200 Processor Data Book 32580B 1: CRT, GPIO and TFT Signals Name TFTD3 TFTD2 TFTD4 TFTD6 TFTD16 TFTD14...
  • Page 74 TFTD2 Note 2 None GPIO20 DOCCS# None GPIO1 IOCS1# PMR[29] = 0 FP_VDD_ON PMR[29] = 1 AMD Geode™ SC2200 Processor Data Book General Configuration Block Add’l Dependencies None None None None Note 1 Note 1 Note 1 Note 1 Note 1...
  • Page 75 GPIO38/IRRX2 AL8 / J31 GPIO39 IOCS1SEL (Select IOCS1). Selects ball functions for IOCS1# or GPIO1. Works in conjunction with PMR[23], see PMR[23] for definition. AMD Geode™ SC2200 Processor Data Book 1: GPIO Signals Add’l Dependencies Name PMR[2] = 0 GPIO14...
  • Page 76 None SOUT3 1: Audio Signal Add’l Dependencies Name FPCI_MON = 0 PC_BEEP FPCI_MON = 1 F_DEVSEL# AMD Geode™ SC2200 Processor Data Book General Configuration Block Add’l Dependencies None Add’l Dependencies PMR[4] = 1 PMR[4] = 0 Add’l Dependencies None None Add’l Dependencies...
  • Page 77 16-bit access to ROM in the Sub-ISA interface is enabled. MCR[14] = 1 inverts the meaning of this register. 0: 8-bit wide ROM. 1: 16-bit wide ROM. Reserved. Write as read. AMD Geode™ SC2200 Processor Data Book 32580B...
  • Page 78 Device Identification Number Register - ID (RO) This register identifies the device. SC2200 = 04h. Offset 3Dh This register identifies the device revision. See AMD Geode™ SC2200 Processor Specification Update document for value. Offset 3Eh-3Fh Configuration Base Address Register - CBA (RO) This register sets the base address of the Configuration block.

  • Page 79: Watchdog

    SUSPA# 32 KHz WDPRES POR# AMD Geode™ SC2200 Processor Data Book • The GX1 module’s internal SUSPA# signal is 1. • The GX1 module’s internal SUSPA# signal is 0 and the WD32KPD bit (Offset 02h[8]) is 0. The 32 KHz input clock is disabled, when: •...

  • Page 80: Table 4-3. Watchdog Registers

    1000: 256 1100: 4096 1001: 512 1101: 8192 1010: 1024 1110: Reserved 1011: 2048 1111: Reserved WATCHDOG Status Register - WDSTS (R/WC) General Configuration Block Reset Value: 0000h Reset Value: 0000h Reset Value: 00h AMD Geode™ SC2200 Processor Data Book...

  • Page 81: High-Resolution Timer

    SUSPA# signal is 0 and the TM27MPD bit is 1. For more information about signal SUSPA# see Section 4.4.2.1 "Usage Hints" on page 85 and the AMD Geode™ GX1 Processor Data Book. The High-Resolution Timer function resides on the internal Fast-PCI bus and its registers are in General Configuration Block address space.

  • Page 82: Table 4-4. High-Resolution Timer Registers

    1: High-Resolution Timer interrupt is enabled. Offset 0Eh-0Fh TIMER Value Register - TMVALUE (RO) TIMER Status Register - TMSTS (R/W) Reserved - RSVD General Configuration Block Reset Value: xxxxxxxxh Reset Value: 00h Reset Value: 00h AMD Geode™ SC2200 Processor Data Book...

  • Page 83: Clock Generators And Plls

    PLL2 and PLL5. V PLL2 Figure 4-2. Clock Generation Block Diagram AMD Geode™ SC2200 Processor Data Book The clock generators are based on 32.768 KHz and 27.000 MHz crystal oscillators. The 32.768 KHz crystal oscillator is described in Section 5.5.2 "RTC Clock Generation" on page 111 (functional description of the RTC).

  • Page 84: Figure 4-3. Recommended Oscillator External Circuitry

    AT-cut or BT-cut 40 Ω 7 pF 10-20 pF User-defined 20 MΩ 100 Ω 3-24 pF 3-24 pF General Configuration Block To other modules Internal External X27I X27O Circuitry Tolerance 50 PPM or better AMD Geode™ SC2200 Processor Data Book...

  • Page 85: Table 4-6. Core Clock Frequency

    0110 66.67 1010 Note: Not all speeds are supported. For information on supported speeds, see Section A.1 "Order Information" on page 447. AMD Geode™ SC2200 Processor Data Book Table 4-6. Core Clock Frequency Internal Fast-PCI Clock Freq. (MHz) Multiplier Value 33.33...
  • Page 86 (Capture Video mode), the video clock is generated by the Display Controller. • If the video data is coming directly from the VIP block (Direct Video mode), the Video Clock is generated by the VIP block. AMD Geode™ SC2200 Processor Data Book...
  • Page 87 Offset 1Eh-1Fh Core Clock Frequency Control Register - CCFC (R/W) This register controls the configuration of the core clock multiplier and the reference clocks. AMD Geode™ SC2200 Processor Data Book Reserved - RSVD PLL Power Control Register - PPCR (R/W)
  • Page 88 MCCM register. 0100: Multiply by 4 0101: Multiply by 5 0110: Multiply by 6 0111: Multiply by 7 1000: Multiply by 8 1001: Multiply by 9 1010: Multiply by 10 Other: Reserved General Configuration Block AMD Geode™ SC2200 Processor Data Book...

  • Page 89: 5.0Superi/O Module

    Serial Port 2 System Wakeup Control Wakeup PWUREQ Events AMD Geode™ SC2200 Processor Data Book 5.0SuperI/O Module Outstanding Features • Full compatibility with ACPI Revision 1.0 requirements. • System Wakeup Control powered by V power-up request and a PME (power management...

  • Page 90: Features

    • Y2K Compliant Clock Sources • 48 MHz clock input • On-chip low frequency clock generator for wakeup • 32.768 KHz crystal with an internal frequency multiplier to generate all required internal frequencies AMD Geode™ SC2200 Processor Data Book SuperI/O Module...

  • Page 91: Module Architecture

    AB2D Real-Time Clock (RTC) Internal Signal AMD Geode™ SC2200 Processor Data Book The central configuration register set supports ACPI com- pliant PnP configuration. The configuration registers are structured as a subset of the Plug and Play Standard Reg- isters, defined in Appendix A of the Plug and Play ISA Specification Version 1.0a by Intel and Microsoft...

  • Page 92: Configuration Structure/Access

    Configuration Register File SuperI/O Module Reference Page 104 Page 106 Page 107 Page 108 Page 109 Page 110 Page 108 SIO Configuration Registers Standard Logical Device Standard Registers Bank Special (Vendor-defined) Select Logical Device Configuration Registers AMD Geode™ SC2200 Processor Data Book...

  • Page 93: Address Decoding

    • When either a hardware or a software reset occurs: — The legacy devices are assigned with their legacy system resource allocation. — The AMD proprietary functions are not assigned with any default resources and the default values of their base addresses are all 00h.

  • Page 94: Standard Configuration Registers

    DMA Channel Select 0 DMA Channel Select 1 Device Specific Logical Device Configuration 1 Device Specific Logical Device Configuration 2 Device Specific Logical Device Configuration 3 Device Specific Logical Device Configuration 4 SuperI/O Module AMD Geode™ SC2200 Processor Data Book...

  • Page 95: Table 5-3. Standard Configuration Registers

    The valid choices are 0-3, where a value of 0 selects DMA channel 0, 1 selects channel 1, etc. A value of 4 indicates that no DMA channel is active. Values 5-7 are reserved. AMD Geode™ SC2200 Processor Data Book write to prevent the values of reserved bits from being changed during write.
  • Page 96 The valid choices are 0-3, where a value of 0 selects DMA channel 0, 1 selects channel 1, etc. A value of 4 indicates that no DMA channel is active. Values 5-7 are reserved. Index F0h-FEh Special (vendor-defined) configuration options. DMA Channel Select 1 (R/W) Logical Device Configuration (R/W) AMD Geode™ SC2200 Processor Data Book SuperI/O Module...

  • Page 97: Table 5-4. Sio Control And Configuration Register Map

    SID. SIO ID SIOCF1. SIO Configuration 1 SIOCF2. SIO Configuration 2 SRID. SIO Revision ID RSVD. Reserved exclusively for AMD use Table 5-5. SIO Control and Configuration Registers Description Index 20h Chip ID. Contains the identity number of the module. The SIO module is identified by the value F5h.

  • Page 98: Table 5-6. Relevant Rtc Configuration Registers

    Real-Time Clock (RTC). Only the last registers (F0h-F3h) are described here (Table 5-7). See Table 5-3 "Standard Configuration Registers" on page 101 for descriptions of the other registers. AMD Geode™ SC2200 Processor Data Book SuperI/O Module Reset Value...

  • Page 99: Table 5-7. Rtc Configuration Registers

    Month Alarm Register Offset Register - MANAO (R/W) Reserved. Month Alarm Register Offset Value. Index F3h Century Register Offset Register - CENO (R/W) Reserved. Century Register Offset Value. AMD Geode™ SC2200 Processor Data Book Table 5-7. RTC Configuration Registers RAM Lock Register - RLR (R/W) 32580B...

  • Page 100: Table 5-8. Relevant Swc Registers

    The logical device registers are maintained, and all wakeup detection mechanisms are functional. described earlier in Table 5-3 "Standard Configuration Reg- isters" on page 101. Table 5-8. Relevant SWC Registers SuperI/O Module Reset Value AMD Geode™ SC2200 Processor Data Book...

  • Page 101: Table 5-9. Relevant Ircp/Sp3 Registers

    0: Disabled. (Default) 1: Enabled (when the device is inactive). AMD Geode™ SC2200 Processor Data Book Only the last register (F0h) is described here (Table 5-10). See Table 5-3 "Standard Configuration Registers" on page 101 for descriptions of the other registers listed.

  • Page 102: Table 5-11. Relevant Serial Ports 1 And 2 Registers

    Serial Ports 1 and 2. Only the last register (F0h) is described here (Table 5-12). See Table 5-3 "Standard Con- figuration Registers" on page 101 for descriptions of the others. AMD Geode™ SC2200 Processor Data Book SuperI/O Module Reset Value Port 1...

  • Page 103: Amd Geode™ Sc2200 Processor Data Book

    0: No internal pull-up resistors on AB1C/AB2C and AB1D/AB2D. (Default) 1: Internal pull-up resistors on AB1C/AB2C and AB1D/AB2D. Reserved. AMD Geode™ SC2200 Processor Data Book ACB1 is designated as LDN 05h and ACB2 as LDN 06h. Table 5-13 lists the configuration registers which affect the ACCESS.bus ports.

  • Page 104: Table 5-15. Relevant Parallel Port Registers

    Parallel Port. Only the last register (F0h) is described here (Table 5-16). See Table 5-3 "Standard Configuration Regis- ters" on page 101 for descriptions of the others. Parallel Port Configuration Register (R/W) SuperI/O Module Reset Value Reset Value: F2h AMD Geode™ SC2200 Processor Data Book...

  • Page 105: Real-Time Clock (Rtc)

    (whether system is on or off). In systems where this is not the case, C1 and C2 should be different by 50% to assure an unbalanced circuit AMD Geode™ SC2200 Processor Data Book These locations may be reassigned, in compliance with Plug and Play requirements.

  • Page 106: Figure 5-6. External Oscillator Connections

    (X32I) 3.3V square wave POWER = 30 KΩ 32.768 KHz Clock Generator = 30 KΩ = 0.1 μF Divider Chain 1 Hz Reset DV2 DV1 DV0 CRA Register Oscillator To other Enable modules X32O AMD Geode™ SC2200 Processor Data Book...
  • Page 107 This mecha- nism enables new time parameters to be loaded in the RTC. AMD Geode™ SC2200 Processor Data Book 32580B Method 2 Access the RTC registers after detection of an Update Ended interrupt.

  • Page 108: Figure 5-8. Power Supply Connections

    (μA) 2.4 3.0 3.6 = 25°C 3.0 3.3 3.6 Operation Mode AMD Geode™ SC2200 Processor Data Book and not...

  • Page 109: Table 5-18. System Power States

    To protect the RTC internal regis- ters from corruption, all inputs are automatically locked out. The lockout condition is asserted when V SBON AMD Geode™ SC2200 Processor Data Book Power-Up Detection When system power is restored after a power failure or power off state (V for a delay of 62 msec (minimum) to 125 msec (maximum) after the RTC switches from battery to system power.

  • Page 110: Figure 5-12. Interrupt/Status Timing

    128 bytes of battery-backed RAM (also called Extended RAM) may be accessed via a second pair of Index and Data registers. Access to the two RAMs may be locked. For details see Table 5-7 on page 105. SuperI/O Module AMD Geode™ SC2200 Processor Data Book...

  • Page 111: Table 5-19. Rtc Register Map

    When bits 7 and 6 are both set to 1, unconditional match is selected. See Section 5.5.2.5 "Alarms" on page 113 for more information about “unconditional” matches. AMD Geode™ SC2200 Processor Data Book these registers is also disabled if bit 7 of the CRD Register is 0.
  • Page 112 SuperI/O Module Reset Type: V Reset Type: V Reset Type: V Reset Type: V Reset Type: V Reset Type: V Reset Type: Bit Specific Reset Type: Bit Specific AMD Geode™ SC2200 Processor Data Book...
  • Page 113 When bits 7 and 6 are both set to one (“11”), unconditional match is selected. (Default) Index Programmable Century Data. Values may be 00 to 99 in BCD format or 00 to 63 in Binary format. AMD Geode™ SC2200 Processor Data Book Table 5-20. RTC Registers (Continued) power-up reset only.

  • Page 114: Table 5-21. Divider Chain Control / Test Selection

    Rate (msec) Chain Output No interrupts 3.906250 7.812500 0.122070 0.244141 0.488281 0.976562 1.953125 3.906250 7.812500 15.625000 31.250000 62.500000 125.000000 250.000000 500.000000 Binary Format 01 to 0C (AM) 81 to 8C (PM) 00 to 17 AMD Geode™ SC2200 Processor Data Book...

  • Page 115: Table 5-24. Standard Ram Map

    The supercap capacitor in the range of 0.047- 0.47 F should supply the power during the battery replacement. AMD Geode™ SC2200 Processor Data Book 32580B 5.5.4 RTC General-Purpose RAM Map Table 5-24.

  • Page 116: System Wakeup Control (Swc)

    Table 5-26 lists the recommended time ranges limits for the different protocols and their applicable ranges. The values are represented in hexadecimal code where the units are of 0.1 ms. Low Limit High Limit SuperI/O Module Low Limit High Limit AMD Geode™ SC2200 Processor Data Book...

  • Page 117: Table 5-27. Banks 0 And 1 - Common Control And Status Register Map

    Table 5-28. Bank 1 - CEIR Wakeup Configuration and Control Register Map Offset Type AMD Geode™ SC2200 Processor Data Book • Bank 0 holds reserved registers. • Bank 1 holds the CEIR Control Registers. The active bank is selected through the Configuration Bank Select field (bits [1:0]) in the Wakeup Configuration Regis- ter (WKCFG).

  • Page 118: Table 5-29. Banks 0 And 1 - Common Control And Status Registers

    Detected wakeup events that are enabled issue a power-up request the or software reset. It enables access to CEIR registers. SuperI/O Module Reset Value: 00h Reset Value: 03h Reset Value: 00h AMD Geode™ SC2200 Processor Data Book...

  • Page 119: Table 5-30. Bank 1 - Ceir Wakeup Configuration And Control Registers

    Bank 1, Offset 09h This register is set to 14h on power-up of V Reserved. CEIR Pulse Change, Range 0, High Limit. AMD Geode™ SC2200 Processor Data Book CEIR Wakeup Control Register - IRWCR (R/W) or software reset. Reserved CEIR Wakeup Address Register - IRWAD (R/W) or software reset.
  • Page 120 CEIR Wakeup Range 3 Registers IRWTR3L Register (R/W) or software reset. IRWTR3H Register (R/W) or software reset. SuperI/O Module Reset Value: 07h Reset Value: 0Bh Reset Value: 50h Reset Value: 64h Reset Value: 28h Reset Value: 32h AMD Geode™ SC2200 Processor Data Book...

  • Page 121: Access.bus Interface

    (8 bits), an Acknowledge signal must follow. The following sections provide further details of this process. AMD Geode™ SC2200 Processor Data Book 32580B During each clock cycle, the slave can stall the master while it handles the previous data or prepares new data.

  • Page 122: Figure 5-15. Access.bus Data Transaction

    Clock Line Held Byte Complete Interrupt Within Low by Receiver Receiver While Interrupt is Serviced 2 3 - 6 SuperI/O Module Stop Condition Transmitter Stays Off Bus During Acknowledge Clock Acknowledge Signal From Receiver AMD Geode™ SC2200 Processor Data Book...

  • Page 123: Master Mode

    1 - 7 Start Address R/W ACK Condition Figure 5-17. A Complete ACCESS.bus Data Transaction AMD Geode™ SC2200 Processor Data Book 5.7.6 Arbitration on the Bus Multiple master devices on the bus require arbitration between their conflicting bus access demands. Control of the bus is initially determined according to address bits and clock cycle.
  • Page 124 Follow the address send sequence, as described pre- viously in "Sending the Address Byte". If the ACB was awaiting handling due to ACBST[3] = 1, clear it only after writing the requested address and direction to ACBSDA. AMD Geode™ SC2200 Processor Data Book SuperI/O Module...
  • Page 125 (on ABD or ABC) is detected, ACBST[5] is set, ACBST[1] is cleared and the device continues to search the received message for a match. AMD Geode™ SC2200 Processor Data Book 32580B If an address match or a global match is detected: The device asserts its ABD pin during the acknowl- edge cycle.

  • Page 126: Table 5-31. Acb Register Map

    ACBADDR. ACB Own Address ACBCTL2. ACB Control 2 Table 5-32. ACB Registers ACB Serial Data Register - ACBSDA (R/W) ACB Status Register - ACBST (R/W) SuperI/O Module Reset Value Reset Value: xxh Reset Value: 00h AMD Geode™ SC2200 Processor Data Book...
  • Page 127 0: Cleared after acknowledge cycle. 1: Negative acknowledge issued on next received byte. Reserved. AMD Geode™ SC2200 Processor Data Book Table 5-32. ACB Registers (Continued) ACB Control Status Register - ACBCST (R/W) ACB Control Register 1 - ACBCTL1 (R/W)
  • Page 128 0: ACB is disabled, ACBCTL1, ACBST and ACBCST registers are cleared, and clocks are halted. 1: ACB is enabled. Table 5-32. ACB Registers (Continued) ACB Own Address Register - ACBADDR (R/W) ACB Control Register 2 - ACBCTL2 (R/W) SuperI/O Module Reset Value: xxh Reset Value: 00h AMD Geode™ SC2200 Processor Data Book...

  • Page 129: Legacy Functional Blocks

    405h Table 5-34. Parallel Port Register Map for Second Level Offset Second Level Offset Type AMD Geode™ SC2200 Processor Data Book 5.8.1 Parallel Port The Parallel Port supports all IEEE1284 standard commu- nication modes: Compatibility (known also as Standard or...

  • Page 130: Table 5-35. Parallel Port Bit Map For First Level Offset

    FIFO FIFO rupt Ser- Full Empty vice Second Level Offset RSVD RSVD EPP Time- out Inter- rupt Mask RSVD RSVD PP DMA Request Active Time PE Inter- ECP DMA Channel nal PU or Number AMD Geode™ SC2200 Processor Data Book...

  • Page 131: Figure 5-18. Uart Mode Register Bank Architecture

    Banks 0 through 3. Offset Type When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 5-38. AMD Geode™ SC2200 Processor Data Book Bank 1 Bank 0 Offset 07h...

  • Page 132: Table 5-38. Bank Selection Encoding

    BGD(L). Baud Generator Divisor Port (Low Byte) BGD(H). Baud Generator Divisor Port (High Byte) EXCR1. Extended Control1 BSR. Bank Select EXCR2. Extended Control 2 RSVD. Reserved RXFLV. RX_FIFO Level TXFLV. TX_FIFO Level SuperI/O Module Bank Selected AMD Geode™ SC2200 Processor Data Book...

  • Page 133: Table 5-41. Bank 3 Register Map

    In SP2 only. When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 5-38 on page 139. AMD Geode™ SC2200 Processor Data Book Table 5-41. Bank 3 Register Map Name MRID.

  • Page 134: Table 5-43. Bank 1 Bit Map

    RSVD PRESL[1:0] Reserved RSVD RSVD Table 5-45. Bank 3 Bit Map Bits MID[3:0] SBRK STKP TXFHT[1:0] RSVD BSR[6:0] (Bank Select) RSVD SuperI/O Module WLS[1:0] RSVD EXT_SL RSVD RFL[4:0] TFL[4:0] RID[3:0] WLS[1:0] TXSR RXSR FIFO_EN AMD Geode™ SC2200 Processor Data Book...

  • Page 135: Figure 5-19. Ircp/Sp3 Register Bank Architecture

    Banks 0 through 7. Offset Type When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 5-47. AMD Geode™ SC2200 Processor Data Book Bank 0 Offset 07h Offset 06h...

  • Page 136: Table 5-47. Bank Selection Encoding

    BGD(H). Baud Generator Divisor Port (High Byte) EXCR1. Extended Control 1 BSR. Bank Select EXCR2. Extended Control 2 RSVD. Reserved TXFLV. TX FIFO Level RXFLV. RX FIFO Level SuperI/O Module Bank Selected Functionality UART + IR IR Only AMD Geode™ SC2200 Processor Data Book...

  • Page 137: Table 5-50. Bank 3 Register Map

    SuperI/O Module Offset Type 04h-07h Offset Type Offset Type AMD Geode™ SC2200 Processor Data Book Table 5-50. Bank 3 Register Map Name MID. Module and Revision Identification SH_LCR. Link Control Shadow SH_FCR. FIFO Control Shadow BSR. Bank Select RSVD. Reserved Table 5-51.

  • Page 138: Table 5-53. Bank 6 Register Map

    LS_IE TXLDL_IE RXHDL_IE MS_IE LS_IE TXLDL_IE RXHDL_IE RXFT IPR[1:0] MS_EV LS_EV/ TXLDL_EV RXHDL_EV TXHLT_EV RSVD TXSR RXSR FIFO_EN WLS[1:0] ISEN/ RILP DCDLP TX_DFR DMA_EN BAD_CRC DDCD TERI DDSR TXHFE S_EOT FEND_INF RXF_TOUT AMD Geode™ SC2200 Processor Data Book RXDA DCTS...

  • Page 139: Table 5-56. Bank 1 Bit Map

    Offset Name TMR(L) TMR(H) IRCR1 BKSE TFRL(L)/ TFRCC(L) TFRL(H)/ TFRCC(H) AMD Geode™ SC2200 Processor Data Book Table 5-56. Bank 1 Bit Map Bits LBGD[7:0] (Low Byte Data) LBGD[15:8] (High Byte Data) RSVD SBRK STKP BSR[6:0] (Bank Select) RSVD Table 5-57. Bank 2 Bit Map...

  • Page 140: Table 5-60. Bank 5 Bit Map

    RXHSC RCDM_DS BSR[6:0] (Bank Select) SIRC[2:0] RSVD IRSL0_DS RXINV IRSL21_DS SuperI/O Module TX_MS MDRS IRMSSL IR_FDPLX BAD_CRC OVR1 RSVD TXCRC_INV TXCRC_DS MPW[3:0] SPW[3:0] FPL[3:0] DFR[4:0] MCFR[4:0] RSVD TXHSC RC_MMD[1:0] IRID3 IRIC[2:0] RSVD AMD Geode™ SC2200 Processor Data Book OVR2 RSVD...

  • Page 141: 6.0Core Logic Module

    • PCI master for AC97 and IDE controllers • Subtractive agent for unclaimed transactions • Supports PCI initiator-to-Sub-ISA cycle translations • PCI-to-Sub-ISA interrupt mapper/translator AMD Geode™ SC2200 Processor Data Book 32580B 6.0Core Logic Module • External PCI bus — Devices internal to the Core Logic module (IDE, Audio, USB, Sub-ISA, etc.) cannot master to memory...

  • Page 142: Module Architecture

    • ACPI compliant power management (includes GPIO interfaces, such as joystick) • Integrated audio controller • Low Pin Count (LPC) Interface Fast-PCI 33-66 MHz PCI Interface 33 MHz Config. Reg. X-Bus Legacy ISA/PIC/PIT/DMA Sub-ISA Core Logic Module AC97 Audio Controller AMD Geode™ SC2200 Processor Data Book...
  • Page 143 The Core Logic module decodes the serial packet after each transmission and performs the power management tasks related to video retrace. For more information on the Serial Packet register refer to the AMD Geode™ GX1 Processor Data Book.

  • Page 144: Ide Controller

    Mode 0 and data timing for Mode 4. The Mode 0 device would have both command and data timings for Mode 0. Note that for the Mode 0 case, the 32-bit timing AMD Geode™ SC2200 Processor Data Book Core Logic Module...

  • Page 145: Register Descriptions

    31 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Memory Region Physical Base Address [31:1] (IDE Data Buffer) Reserved AMD Geode™ SC2200 Processor Data Book mand register bit 0 = 1), data transfer proceeds until each PRD in the PRD table has been transferred. The bus mas- ter does not cache PRDs.

  • Page 146: Table 6-2. Ultradma/33 Signal Definitions

    Also listed in the bit formats are recommended values for both Multiword DMA Modes 0-2 and UltraDMA/33 Modes 0-2. Note that these are only recommended settings and are not 100% tested. Core Logic Module AMD Geode™ SC2200 Processor Data Book...

  • Page 147: Universal Serial Bus

    — DOCR# is asserted on memory read transactions from DOCCS# window (i.e., when both DOCCS# and MEMR# are active, DOCR# is active; otherwise, it is inactive). AMD Geode™ SC2200 Processor Data Book 32580B • DOCW — DOCW# is asserted on memory write transactions to DOCCS# window (i.e., when both DOCCS# and...

  • Page 148: Figure 6-2. Non-Posted Fast-Pci To Isa Access

    PCI cycles from occupying too much band- width and allows access to other PCI traffic. Figure 6-3 on page 157 shows the relationship of PCI cycles to an ISA cycle with PCI delayed transactions enabled. AMD Geode™ SC2200 Processor Data Book Core Logic Module...

  • Page 149: Figure 6-3. Pci To Isa Cycles With Delayed Transaction Enabled

    PCI data bus. When the DMA requestor is the bus owner, the Core Logic module allows 8/16-bit data transfer between the Sub-ISA bus and the PCI data bus. AMD Geode™ SC2200 Processor Data Book 32580B 6.2.5.4 I/O Recovery Delays...

  • Page 150: Figure 6-4. Isa Dma Read From Pci Memory

    PCI cycle, asserts FRAME#, and negates an internal IOCHRDY. This assures the DMA cycle does not complete before the PCI cycle has provided or accepted the data. IOCHRDY is internally asserted when IRDY# and TRDY# are sampled active. AMD Geode™ SC2200 Processor Data Book Core Logic Module...

  • Page 151: Table 6-3. Cycle Multiplexed Pci / Sub-Isa Balls

    74HCT245 or 74FCT245 type transceivers. The RD# (an AND of IOR#, MEMR#) signal can be used as DIR control while TRDE# is used as enable control. AMD Geode™ SC2200 Processor Data Book Table 6-3. Cycle Multiplexed PCI / Sub-ISA Balls AD10...

  • Page 152: Figure 6-6. Pci Change To Sub-Isa And Back

    Each channel can transfer data in 128 KB pages. Channels 5, 6, and 7 transfer 16-bit WORDs on even byte boundaries only. Channels 5 through 7 are not supported. AMD Geode™ SC2200 Processor Data Book Core Logic Module...
  • Page 153 The transfer type selected defines the method used to transfer a byte or WORD during one DMA bus cycle. AMD Geode™ SC2200 Processor Data Book 32580B For read transfer types, the Core Logic module reads data from memory and write it to the I/O device associated with the DMA channel.

  • Page 154: Figure 6-7. Pit Timer

    PIT state by reading the PIT’s counter and write only registers. The read sequence for the shadow register is listed in F0 Index BAh (see Table 6-29 on page 198). AMD Geode™ SC2200 Processor Data Book Core Logic Module IRQ0 F0 Index 50h[4]...

  • Page 155: Figure 6-8. Pic Interrupt Controllers

    IRQ14 (muxed with TFTD1), and IRQ9 (muxed with IDE_DATA6) More of the IRQs are available through the use of SERIRQ (muxed with GPIO39) function. See Table 6-4. AMD Geode™ SC2200 Processor Data Book Table 6-4. PIC Interrupt Mapping Master IRQ0...

  • Page 156: Figure 6-9. Pci And Irq Interrupt Mapping

    A20M# state and the SMI handler sets the A20M# state inside the GX1 module. This method is used for both the Port 092h (PS/2) and Port 061h (key- board) methods of controlling A20M#. AMD Geode™ SC2200 Processor Data Book Core Logic Module Level/Edge Sensitivity...

  • Page 157: Keyboard Support

    Bit 2 = ERR_EN (PERR#/SERR# Enable) Bit 3 = IOCHK_EN (IOCHK Enable) I/O Port 070h: RTC Index Register (WO) Bit 72 = NMI (NMI Enable) AMD Geode™ SC2200 Processor Data Book 6.2.8 Keyboard Support The Core Logic module can actively decode the keyboard controller I/O Ports 060h, 062h, 064h and 066h, and gener- ate an LPC bus cycle.

  • Page 158: Power Management Logic

    In this state, the GX1 module is in Suspend Refresh mode (for details, see the Power Management section of the AMD Geode™ GX1 Processor Data Book, and Section 6.2.9.5 "Usage Hints" on page 169). PCI arbitration should be disabled prior entering the C3...

  • Page 159: Table 6-5. Wakeup Events Capability

    IRRX1 (Infrared) GPWIO[2:0] RI2# (UART2) Temporarily exits state. AMD Geode™ SC2200 Processor Data Book decide which other system devices to power off with the PWRCNT1 pin. No reset is performed, when exiting this state. The SC2200 keeps all context in this state. This state corresponds to ACPI sleep state S1, with lower power and longer wake time than in SL1.

  • Page 160: Table 6-7. Power Planes Vs. Sleep/Global States

    Event Power Button Power Button Override Bus Master Request Thermal Monitoring On or Off ACPI Timer On or Off GPIO SDATA_IN2 (AC97) IRRX1 RI2# On or Off GPWIO Internal SMI signal Core Logic Module AMD Geode™ SC2200 Processor Data Book...
  • Page 161 • When SCI_EN bit is 0, ONCTL# and PWRCNT[2:1] are de-asserted immediately regardless of the PWRBTN_EN bit. AMD Geode™ SC2200 Processor Data Book 32580B Power Button Override When PWRBTN# is 0 for more than four seconds, ONCTL# and PWRCNT[2:1] are de-asserted (i.e., the system transi- tions to the SL5 state, “Soft Off”).
  • Page 162 Video activity is defined as any access to the VGA register space, the VGA frame buffer, the graphics accelerator control registers and the configured graphics frame buffer. AMD Geode™ SC2200 Processor Data Book Core Logic Module 6.2.10.3 "Peripheral...
  • Page 163 If F0 Index 96h[1] = 1: Disable Suspend Modulation when an SMI occurs until a read to the SMI Speedup Disable register (F1BAR0+I/O Offset 08h). AMD Geode™ SC2200 Processor Data Book 32580B The SMI Speedup Disable register prevents VSA software from entering Suspend Modulation while operating in SMM.
  • Page 164 F1BAR1+I/O Offset 1Ch) provides the ACPI counter. The counter counts at 14.31818/4 MHz (3.579545 MHz). If SMI generation is enabled (F0 Index 83h[5] = 1), an SMI or SCI is generated when bit 23 toggles. AMD Geode™ SC2200 Processor Data Book Core Logic Module...

  • Page 165: Figure 6-11. General Purpose Timer And Udef Trap Smi Tree Example

    Other_SMI Top Level Figure 6-11. General Purpose Timer and UDEF Trap SMI Tree Example AMD Geode™ SC2200 Processor Data Book These two registers are identical except that reading the register at F1BAR0+I/O Offset 02h clears the status. Since all SMI sources report to the Top Level SMI Status register, many of its bits combine a large number of events requiring a second level of SMI status reporting.

  • Page 166: Table 6-9. Device Power Management Programming Summary

    F1BAR0+I/O Offset 04h[4] 88h[7:0], 89h[7:0], 8Bh[4] F1BAR0+I/O Offset 04h[0] 8Ah[7:0], 8Bh[5,3,2] F1BAR0+I/O Offset 04h[1] 94h[15:0], 96h[2:0] 8Dh[7:0], A8h[15:0] 8Ch[7:0] AMD Geode™ SC2200 Processor Data Book Core Logic Module Second Level SMI Status/With Clear F5h[3] F5h[2] F5h[1] F5h[7] F1BAR0+I/O Offset 02h[6]...

  • Page 167: Gpio Interface

    16-Bit output to codec. Slot in use is determined by F3BAR0+Memory Offset 08h[19]. 6 or 11 16-Bit input from codec. Slot in use is determined by F3BAR0+Memory Offset 08h[20]. AMD Geode™ SC2200 Processor Data Book 32580B • Trap accesses for MIDI UART interface at I/O Port 300h- 301h or 330h-331h.

  • Page 168: Table 6-11. Physical Region Descriptor Format

    SMI generated by the EOP from the first PRD allows the software to refill Audio Buffer_1. The second SMI refills Audio Buffer_2. The third SMI refills Audio Buffer_1 and so on. Byte 2 Reserved Core Logic Module Byte 1 Byte 0 Size [15:1] AMD Geode™ SC2200 Processor Data Book...

  • Page 169: Figure 6-12. Prd Table Example

    EOT = 0 EOP = 0 JMP = 1 AMD Geode™ SC2200 Processor Data Book Table Address register is incremented by 08h and is now pointing to PRD_3. The SMI Status register is read to clear the End of Page status flag. Since Audio Buffer_1 is now empty, the software can refill it.

  • Page 170: Figure 6-13. Ac97 V2.0 Codec Signal Connections

    The bit formats for these registers are given in Table 6-38 "F3BAR0+Memory Offset: Audio Configuration Registers" on page 273. BIT_CLK XTAL_I SYNC Codec1 PC_BEEP SDATA_OUT SDATA_IN BIT_CLK XTAL_I Codec2 SYNC (Optional) PC_BEEP SDATA_OUT SDATA_IN2 AMD Geode™ SC2200 Processor Data Book Core Logic Module...
  • Page 171 • I/O Trap SMI and Fast Write Status Register (F3BAR0+Memory Offset 14h) • I/O Trap SMI Enable Register (F3BAR0+Memory Offset 18h) AMD Geode™ SC2200 Processor Data Book 32580B Audio SMI Status Reporting Registers: The Top SMI Status Mirror and Status registers are the top...

  • Page 172: Figure 6-14. Audio Smi Tree Example

    Offset 14h Read to Clear to determine third-level source of SMI Bits [31:14] Other_RO Bit 13 SMI_SC/FM_TRAP Bit 12 Take SMI_DMA_TRAP Appropriate Bit 11 Action SMI_MPU_TRAP Bit 10 SMI_SC/FM_TRAP Bits [9:0] Other_RO Third Level AMD Geode™ SC2200 Processor Data Book...

  • Page 173: Figure 6-15. Typical Setup

    The mother- board BIOS should be able to configure all devices at boot. AMD Geode™ SC2200 Processor Data Book 32580B • Support desktop and mobile implementations. • Enable support of a variable number of wait states.

  • Page 174: Table 6-12. Cycle Types

    • Only 8- or 16-bit DMA, depending on channel number. Does not support the optional larger transfer sizes. • Only one external DRQ pin. AMD Geode™ SC2200 Processor Data Book Core Logic Module (Bytes) 1 or 2 1 or 2...
  • Page 175 The device number depends upon the IDSEL Strap Override bit (F5BAR0+I/O Offset 04h[0]). This bit allows selection of the address lines to be used as the IDSEL. By Default: IDSEL = AD28 (1001 0) for F0-F5, AD29 (1001 1) for PCIUSB. AMD Geode™ SC2200 Processor Data Book 6.3.1...

  • Page 176: Register Summary

    Page 203 Page 204 Page 204 FFFFFFFFh Page 204 Page 204 Page 205 Page 205 Page 206 Page 206 Page 206 Page 207 Page 208 Page 208 Page 208 00000000h Page 208 Page 209 AMD Geode™ SC2200 Processor Data Book...
  • Page 177 Suspend Notebook Command Register B0h-B3h Reserved Floppy Port 3F2h Shadow Register Floppy Port 3F7h Shadow Register Floppy Port 1F2h Shadow Register Floppy Port 1F7h Shadow Register AMD Geode™ SC2200 Processor Data Book 32580B Reset Reference Value (Table 6-29) 0000FFF0h Page 209...
  • Page 178 Page 226 00000000h Page 227 00000000h Page 227 Page 227 Page 227 Page 228 Page 228 Page 228 Page 228 Page 228 Page 228 Page 228 Page 229 Page 230 Page 231 Page 232 AMD Geode™ SC2200 Processor Data Book...

  • Page 179: Table 6-15. F0Bar0: Gpio Support Registers Summary

    LAD_D0 — LPC Address Decode 0 Register 18h-1Bh LAD_D1 — LPC Address Decode 1 Register 1Ch-1Fh LPC_ERR_SMI — LPC Error SMI Register 20h-23h LPC_ERR_ADD — LPC Error Address Register AMD Geode™ SC2200 Processor Data Book 32580B Reset Reference Value (Table 6-30) FFFFFFFFh...

  • Page 180: Table 6-17. F1: Pci Header Registers For Smi Status And Acpi Support Summary

    Value (Table 6-33) 0000h Page 246 0000h Page 247 0000h Page 249 0000h Page 250 0000h Page 250 Page 250 xxxxxxxxh Page 250 0000h Page 251 0000h Page 251 00000000h Page 252 Page 254 AMD Geode™ SC2200 Processor Data Book...

  • Page 181: Table 6-19. F1Bar1: Acpi Support Registers Summary

    GPWIO Data Register Reserved 18h-1Bh ACPI SCI_ROUTING Register 1Ch-1Fh PM_TMR — ACPI Timer Register PM2_CNT — PM2 Control Register 21h-FFh Not Used AMD Geode™ SC2200 Processor Data Book 32580B Reset Reference Value (Table 6-34) 00000000h Page 255 Page 255 Page 255...

  • Page 182: Table 6-20. F2: Pci Header Registers For Ide Controller Support Summary

    100Bh Page 266 0502h Page 266 Page 266 00009172h Page 267 00077771h Page 268 00009172h Page 269 00077771h Page 269 00009172h Page 269 00077771h Page 269 00009172h Page 269 00077771h Page 269 Page 269 AMD Geode™ SC2200 Processor Data Book...

  • Page 183: Table 6-21. F2Bar4: Ide Controller Support Registers Summary

    VSA audio interface control register block (summarized in Table 6-23). 14h-2Bh Reserved 2Ch-2Dh Subsystem Vendor ID 2Eh-2Fh Subsystem ID 30h-FFh Reserved AMD Geode™ SC2200 Processor Data Book 32580B Name 00000000h 00000000h 040100h 00000000h Reset Reference Value (Table 6-36)

  • Page 184: Table 6-23. F3Bar0: Audio Support Registers Summary

    Page 283 Page 283 00000000h Page 283 Page 284 Page 284 Page 284 00000000h Page 284 Page 285 Page 285 Page 285 00000000h Page 285 Page 286 Page 286 Page 286 00000000h Page 286 AMD Geode™ SC2200 Processor Data Book...

  • Page 185: Table 6-24. F5: Pci Header Registers For X-Bus Expansion Support Summary

    Width I/O Offset (Bits) Type Name 00h-03h I/O Control Register 1 04h-07h I/O Control Register 2 08h-0Bh I/O Control Register 3 AMD Geode™ SC2200 Processor Data Book 32580B Reset Reference Value (Table 6-39) 100Bh Page 287 0505h Page 287 0000h...

  • Page 186: Table 6-26. Pciusb: Usb Pci Configuration Register Summary

    Page 293 Page 293 Page 293 00000000h Page 294 Page 294 0E11h Page 294 A0F8h Page 294 Page 294 Page 294 Page 294 Page 294 Page 294 000F0000h Page 294 Page 294 Page 294 AMD Geode™ SC2200 Processor Data Book...

  • Page 187: Table 6-27. Usb_Bar: Usb Controller Registers Summary

    58h-5Bh HcRhPortStatus[2] 5Ch-5Fh HcRhPortStatus[3] 60h-9Fh Reserved 100h-103h HceControl 104h-107h HceInput 108h-10Dh HceOutput 10Ch-10Fh HceStatus AMD Geode™ SC2200 Processor Data Book 32580B Reference Reset Value (Table 6-42) 00000110h Page 295 00000000h Page 295 00000000h Page 295 00000000h Page 295 00000000h Page 296...

  • Page 188: Table 6-28. Isa Legacy I/O Register Summary

    Page 309 Page 309 Page 309 Page 309 Page 309 Page 310 Page 310 Page 310 Page 310 Page 310 Page 310 Page 310 Page 310 Page 310 Page 310 Page 310 Page 310 AMD Geode™ SC2200 Processor Data Book...
  • Page 189 Secondary IDE Registers 376h-377h 1F0-1F7h/ Primary IDE Registers 3F6h-3F7h 4D0h Interrupt Edge/Level Select Register 1 4D1h Interrupt Edge/Level Select Register 2 AMD Geode™ SC2200 Processor Data Book 32580B Reference Page 310 Page 310 Page 310 Page 310 Page 311 Page 311...

  • Page 190: Chipset Register Space

    (described in Section 6.4.1.1 "GPIO Support Registers" on page 233 and Section 6.4.1.2 "LPC Support Registers" on page 237). Vendor Identification Register (RO) Device Identification Register (RO) PCI Command Register (R/W) AMD Geode™ SC2200 Processor Data Book Reset Value: 100Bh Reset Value: 0500h Reset Value: 000Fh...
  • Page 191 Fast Back-to-Back Capable. (Read Only) Enables the Core Logic module, as a target, to accept fast back-to-back trans- actions. 0: Disable. 1: Enable. This bit is always set to 1. Reserved. (Read Only) Must be set to 0 for future use. AMD Geode™ SC2200 Processor Data Book PCI Status Register (R/W) 32580B Reset Value: 0280h...
  • Page 192 Reset Value: 00h Reset Value: 060100h Reset Value: 00h Reset Value: 00h Reset Value: 80h Reset Value: 00h Reset Value: 00000001h Reset Value: 00000001h Reset Value: 00h Reset Value: 100Bh Reset Value: 0500h Reset Value: 00h AMD Geode™ SC2200 Processor Data Book...
  • Page 193 1: Enable. Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9]. Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[5]. AMD Geode™ SC2200 Processor Data Book PCI Function Control Register 1 (R/W) PCI Function Control Register 2 (R/W)
  • Page 194 Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Reserved Delayed Transactions Register (R/W) Reset Control Register (R/W) Reset Value: 00h Reset Value: 02h Reset Value: 01h AMD Geode™ SC2200 Processor Data Book...
  • Page 195 F0BAR0 (PCI Function 0, Base Address Register 0). F0BAR0, pointer to I/O mapped GPIO configuration registers. 0: Disable. 1: Enable. Reserved. Must be set to 0. AMD Geode™ SC2200 Processor Data Book Reserved PCI Functions Enable Register (R/W) Miscellaneous Enable Register (R/W)
  • Page 196 100: Divide by 5 101: Divide by 6 110: Divide by 7 111: Divide by 8 ISA I/O Recovery Control Register (R/W) Reset Value: 00h Reset Value: FFFFFFFFh Reset Value: 7Bh Reset Value: 40h AMD Geode™ SC2200 Processor Data Book...
  • Page 197 0: Disable. 1: Enable. This bit must be set to 1. SMI status is reported at F1BAR0+I/O Offset 00h/02h[7]. Index 54h-59h AMD Geode™ SC2200 Processor Data Book ROM/AT Logic Control Register (R/W) Alternate CPU Support Register (R/W) Reserved 32580B Reset Value: 98h...
  • Page 198 1: Positive. Positively decoded IDE addresses are forwarded to the internal IDE controller and then to the IDE bus. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Decode Control Register 1 (R/W) Decode Control Register 2 (R/W) AMD Geode™ SC2200 Processor Data Book Reset Value: 01h Reset Value: 20h...
  • Page 199 SUSP_3V Shut Down PLL4. Allow internal SUSP_3V to shut down PLL4 0: Clock generator is stopped when internal SUSP_3V is active. 1: Clock generator continues working when internal SUSP_3V is active. AMD Geode™ SC2200 Processor Data Book PCI Interrupt Steering Register 1 (R/W) 0100: IRQ4...
  • Page 200 Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Reserved ROM Mask Register (R/W) IOCS1# Base Address Register (R/W) IOCS1# Control Register (R/W) Reset Value: 00h Reset Value: 0000FFF0h Reset Value: 0000h Reset Value: 00h AMD Geode™ SC2200 Processor Data Book...
  • Page 201 DOCCS# Memory Address Range. This 19-bit mask is used to qualify accesses on which DOCCS# is asserted by mask- ing the upper 19 bits of the incoming PCI address (AD[31:13]). AMD Geode™ SC2200 Processor Data Book 01111: 16 Bytes 11111: 32 Bytes All other combinations are reserved.
  • Page 202 Second level SMI status is reported at F0 Index 85h/F5h[7]. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Power Management Enable Register 1 (R/W) Power Management Enable Register 2 (R/W) Reset Value: 00h Reset Value: 00h AMD Geode™ SC2200 Processor Data Book...
  • Page 203 — COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is excluded). — COM3: I/O Port 3E8h-3EFh. — COM4: I/O Port 2E8h-2EFh. Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[2]. AMD Geode™ SC2200 Processor Data Book 32580B...
  • Page 204 Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[3]. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Power Management Enable Register 3 (R/W) Reset Value: 00h AMD Geode™ SC2200 Processor Data Book...
  • Page 205 0: Disable. 1: Enable. Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 87h/F7h[6]. AMD Geode™ SC2200 Processor Data Book Power Management Enable Register 4 (R/W) 32580B Reset Value: 00h...
  • Page 206 1) Ensure that GPWIO0 is enabled as an input: F1BAR1+I/O Offset 15h[0] = 0. 2) Set F1BAR1+I/O Offset 15h[4] to 1. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 AMD Geode™ SC2200 Processor Data Book Reset Value: 00h...
  • Page 207 Primary Hard Disk Idle Timer Timeout. Indicates whether or not an SMI was caused by expiration of Primary Hard Disk Idle Timer Count Register (F0 Index 98h). 0: No. 1: Yes. To enable SMI generation, set F0 Index 81h[0] to 1. AMD Geode™ SC2200 Processor Data Book 32580B Reset Value: 00h...
  • Page 208 Primary Hard Disk Access Trap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to the primary hard disk. 0: No. 1: Yes. To enable SMI generation, set F0 Index 82h[0] to 1. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 AMD Geode™ SC2200 Processor Data Book Reset Value: 00h...
  • Page 209 See Section 6.2.10.3 "Peripheral Power Man- agement" on page 172 for a discussion on the limitations of producing count error with small values.” AMD Geode™ SC2200 Processor Data Book 32580B...
  • Page 210 Any access to the primary hard disk address range selected in F0 Index 93h[5], reloads General Purpose Timer 1. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 AMD Geode™ SC2200 Processor Data Book Reset Value: 00h...
  • Page 211 This speedup mechanism allows instantaneous response to video activity for full speed during video processing calcula- tions. A typical value here would be 50 msec to 100 msec. AMD Geode™ SC2200 Processor Data Book IRQ Speedup Timer Count Register (R/W)
  • Page 212 VGA Timer Count Register (R/W) Reserved Miscellaneous Device Control Register (R/W) Suspend Modulation Register (R/W) Suspend Configuration Register (R/W) Reset Value: 00h Reset Value: 00h Reset Value: 00h Reset Value: 0000h Reset Value: 00h AMD Geode™ SC2200 Processor Data Book...
  • Page 213 This counter uses a 1 second timebase. To enable this timer, set F0 Index 81h[2] = 1. Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[2]. AMD Geode™ SC2200 Processor Data Book Reserved Floppy Disk Idle Timer Count Register (R/W)
  • Page 214 Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Video Idle Timer Count Register (R/W) Video Overflow Count Register (R/W) Reserved Reset Value: 0000h Reset Value: 0000h Reset Value: 0000h Reset Value: 0000h Reset Value: 0000h Reset Value: 0000h Reset Value: 00h AMD Geode™ SC2200 Processor Data Book...
  • Page 215 This register is a copy of an I/O register which cannot safely be directly read. The value in this register is not deterministic of when the register is being read. It is provided here to assist in a Suspend-to-Disk operation. AMD Geode™ SC2200 Processor Data Book CPU Suspend Command Register (WO)
  • Page 216 Bits [7:6] of the command words are not used. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 DMA Shadow Register (RO) PIC Shadow Register (RO) PIT Shadow Register (RO) AMD Geode™ SC2200 Processor Data Book Reset Value: xxh Reset Value: xxh Reset Value: xxh...
  • Page 217 Index CCh Memory or I/O Mapped. Determines how User Defined Device 1 is mapped. 0: I/O. 1: Memory. AMD Geode™ SC2200 Processor Data Book RTC Index Shadow Register (RO) Clock Stop Control Register (R/W) 0100: 4 msec 1000: 8 msec...
  • Page 218 User Defined Device 3 Control Register (R/W) Reserved Software SMI Register (WO) Reserved Timer Test Register (R/W) Reserved Reset Value: 00h Reset Value: 00h Reset Value: 00h Reset Value: 00h Reset Value: 00h Reset Value: 00h Reset Value: 00h AMD Geode™ SC2200 Processor Data Book...
  • Page 219 Defined Device 1 (UDEF1) Idle Timer Count Register (F0 Index A0h). 0: No. 1: Yes. To enable SMI generation, set F0 Index 81h[4] = 1. AMD Geode™ SC2200 Processor Data Book Second Level PME/SMI Status Register 1 (RC) Second Level PME/SMI Status Register 2 (RC) 32580B...
  • Page 220 0: No. 1: Yes. To enable SMI generation, set F0 Index 82h[2] =1. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Second Level PME/SMI Status Register 3 (RC) Reset Value: 00h AMD Geode™ SC2200 Processor Data Book...
  • Page 221 0: No. 1: Yes. This SMI event can only occur while in 3V Suspend and an RTC interrupt occurs and F1BAR1+I/O Offset 0Ch[0] = 0. AMD Geode™ SC2200 Processor Data Book Second Level PME/SMI Status Register 4 (RC) 32580B Reset Value: 00h...
  • Page 222 ACPI Timer SMI Status. Indicates whether or not an SMI was caused by an ACPI Timer (F1BAR0+I/O Offset 1Ch or F1BAR1+I/O Offset 1Ch) MSB toggle. 0: No. 1: Yes. To enable SMI generation, set F0 Index 83h[5] = 1. Index F8h-FFh Reserved Reset Value: 00h AMD Geode™ SC2200 Processor Data Book...

  • Page 223: Table 6-30. F0Bar0+I/O Offset: Gpio Configuration Registers

    1: Corresponding GPIO signal driven or released to high (according to buffer type and static pull-up selection) when output enabled. AMD Geode™ SC2200 Processor Data Book ration registers are located. Table 6-29 gives the bit formats of I/O mapped registers accessed through F0BAR0.
  • Page 224 Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 GPDI1 — GPIO Data In 1 Register (RO) GPST1 — GPIO Status 1 Register (R/W1C) Reset Value: FFFFFFFFh Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h AMD Geode™ SC2200 Processor Data Book...
  • Page 225 0: Falling edge or low level input. (Default) 1: Rising edge or high level input. See the note in the description of this register for more information about the default value of this bit. AMD Geode™ SC2200 Processor Data Book 32580B 010000 = GPIO16 (ball V31)
  • Page 226 This bit is level-sensitive and must be cleared after the reset is enabled (normal operation requires this bit to be 0). Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 GPIO Reset Control Register (R/W) AMD Geode™ SC2200 Processor Data Book Reset Value: 00000000h...

  • Page 227: Table 6-31. F0Bar1+I/O Offset: Lpc Interface Configuration Registers

    IRQ9 Source. Selects the interface source of the IRQ9 signal. 0: ISA - IRQ9 (ball AA3). 1: LPC - SERIRQ (ball J31). AMD Geode™ SC2200 Processor Data Book 32580B The LPC Interface supports all features described in the LPC bus specification 1.0, with the following exceptions: •...
  • Page 228 IRQ15 Polarity. If LPC is selected as the interface source for IRQ15 (F0BAR1+I/O Offset 00h[15] = 1), this bit allows signal polarity selection. 0: Active high. 1: Active low. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 AMD Geode™ SC2200 Processor Data Book Reset Value: 00000000h...
  • Page 229 0: Active high. 1: Active low. IRQ3 Polarity. If LPC is selected as the interface source for IRQ3 (F0BAR1+I/O Offset 00h[3] = 1), this bit allows signal polarity selection. 0: Active high. 1: Active low. AMD Geode™ SC2200 Processor Data Book 32580B...
  • Page 230 0110: 23 frames 1010: 27 frames 0111: 24 frames 1011: 28 frames DRQ_SRC — DRQ Source Register (R/W) Reset Value: 00000000h 1100: 29 frames 1101: 30 frames 1110: 31 frames 1111: 32 frames Reset Value: 00000000h AMD Geode™ SC2200 Processor Data Book...
  • Page 231 LPC Audio Addressing. Audio addresses. See bit 16 for decode. Address selection made via F0BAR1+I/O Offset 14h[9:8]. LPC Serial Port 1 Addressing. Serial Port 1 addresses. See bit 16 for decode. Address selection made via F0BAR1+I/O Offset 14h[7:5]. AMD Geode™ SC2200 Processor Data Book 32580B Reset Value: 00000000h...
  • Page 232 01: 278h-27Fh (+678h-67Fh for ECP) (Note) 11: Reserved Reset Value: 00080020h 1100: 20Ch 1101: 20Dh 1110: 20Eh 1111: 20Fh 1100: 20Ch 1101: 20Dh 1110: 20Eh 1111: 20Fh 110: 338h-33Fh 111: 3E8h-3EFh 110: 338h-33Fh 111: 3E8h-3EFh AMD Geode™ SC2200 Processor Data Book...
  • Page 233 Writing a 1 to this bit also clears the top level status bit as long as bit 6 of this register is cleared. LPC Multiple Errors Status. Indicates whether or not multiple errors have occurred on LPC. 0: No. 1: Yes. Write 1 to clear. AMD Geode™ SC2200 Processor Data Book 32580B Reset Value: 00000000h Reset Value: 00000080h...
  • Page 234 1: Yes. Write 1 to clear. Offset 20h-23h LPC_ERR_ADD — LPC Error Address Register (RO) 31:0 LPC Error Address. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 AMD Geode™ SC2200 Processor Data Book Reset Value: 00000000h...

  • Page 235: Table 6-32. F1: Pci Header Registers For Smi Status And Acpi Support

    Enable. (Write Only) This bit must be set to 1 to enable access to ACPI Support Registers. Index 44h-FFh AMD Geode™ SC2200 Processor Data Book Located in the PCI Header registers of F1 are two Base Address Registers (F1BARx) used for pointing to the regis- ter spaces designated for SMI status and ACPI support, described later in this section.

  • Page 236: Table 6-33. F1Bar0+I/O Offset: Smi Status Registers

    Core Logic Module - SMI Status and ACPI Registers - Function 1 The registers at F1BAR0+I/O Offset 50h-FFh can also be accessed F0 Index 50h-FFh. The preferred method is to program these registers through the F0 register space. AMD Geode™ SC2200 Processor Data Book Reset Value: 0000h...
  • Page 237 The next level (second level) of SMI status is reported in the SuperI/O module. See Table 5-29 "Banks 0 and 1 - Common Control and Status Registers" on page 125 for details. AMD Geode™ SC2200 Processor Data Book Top Level PME/SMI Status Register (RO/RC)
  • Page 238 (except for GP timers, UDEFx and PCI/ISA function traps which are reported in bit 9). 0: No. 1: Yes. The next level (second level) of SMI status is at F0 Index 84h/F4h-87h/F7h. Core Logic Module - SMI Status and ACPI Registers - Function 1 AMD Geode™ SC2200 Processor Data Book...
  • Page 239 Purpose Timer 1 (F0 Index 88h). 0: No. 1: Yes. To enable SMI generation, set F0 Index 83h[0] = 1. AMD Geode™ SC2200 Processor Data Book Second Level General Traps & Timers PME/SMI Status Mirror Register (RO) 32580B Reset Value: 0000h...
  • Page 240 TMR_VAL. This field returns the running count of the power management timer. Core Logic Module - SMI Status and ACPI Registers - Function 1 Reserved ACPI Timer Register (RO) AMD Geode™ SC2200 Processor Data Book Reset Value: 0000h Reset Value: 0000h Reset Value: 00h...
  • Page 241 SLP_EN SMI Status. Indicates whether or not an SMI was caused by a write of 1 to the ACPI SLP_EN bit (F1BAR1+I/O Offset 0Ch[13]). 0: No. 1: Yes. To enable SMI generation, set F1BAR1+I/O Offset 18h[9] to 1 (default). AMD Geode™ SC2200 Processor Data Book Second Level ACPI PME/SMI Status Mirror Register (RO) 32580B Reset Value: 0000h...
  • Page 242 EXT_SMI0 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI0. 0: No. 1: Yes. To enable SMI generation, set bit 0 to 1. Core Logic Module - SMI Status and ACPI Registers - Function 1 External SMI Register (R/W) AMD Geode™ SC2200 Processor Data Book Reset Value: 00000000h...
  • Page 243 EXT_SMI5 SMI Enable. When this bit is asserted, allow EXT_SMI5 to generate an SMI on negative-edge events. 0: Disable. 1: Enable. Top level SMI status is reported at F1BAR0+00h/02h[10]. Second level SMI status is reported at bits 21 (RC) and 13 (RO). AMD Geode™ SC2200 Processor Data Book 32580B...
  • Page 244 50h-FFh figuration Registers for GPIO and LPC Support" on page 198 for more information about these registers. Core Logic Module - SMI Status and ACPI Registers - Function 1 Not Used AMD Geode™ SC2200 Processor Data Book Reset Value: 00h...

  • Page 245: Table 6-34. F1Bar1+I/O Offset: Acpi Support Registers

    1: Disable. (No debounce) GPWIO2 pin does not have debounce capability. Reserved. Must be set to 0. AMD Geode™ SC2200 Processor Data Book are located. Table 6-34 shows the I/O mapped ACPI Sup- port registers accessed through F1BAR1. P_CNT — Processor Control Register (R/W)
  • Page 246 For the PME to generate an SCI, set F1BAR1+I/O Offset 0Ah[5] to 1 and F1BAR1+I/O Offset 0Ch[0] to 1. (See Note 2 in the general description of this register.) Write 1 to clear. Core Logic Module - SMI Status and ACPI Registers - Function 1 AMD Geode™ SC2200 Processor Data Book Reset Value: 0000h...
  • Page 247 If F1BAR1+I/O Offset 18h[9] = 1, an SMI is generated when SLP_EN is set. Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[2]. Second level SMI status is reported at F1BAR0+I/O Offset 20h/22h[2]. AMD Geode™ SC2200 Processor Data Book PM1A_CNT — PM1A Control Register (R/W) 32580B...
  • Page 248 Core Logic Module - SMI Status and ACPI Registers - Function 1 100: Sleep State SL4 101: Sleep State SL5 (Soft off) 110: Reserved 111: Reserved ACPI_BIOS_STS Register (R/W) ACPI_BIOS_EN Register (R/W) AMD Geode™ SC2200 Processor Data Book Reset Value: 00h Reset Value: 00h Reset Value: xxxxh...
  • Page 249 Write 1 to clear. For the PME to generate an SCI, set F1BAR1+I/O Offset 12h[4] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note 2 in the general description of this register above.) AMD Geode™ SC2200 Processor Data Book 32580B...
  • Page 250 THRM_EN. Allow THRM# to generate an SCI. 0: Disable. 1: Enable SMI_EN. Allow SMI events to generate an SCI. 0: Disable. 1: Enable. Core Logic Module - SMI Status and ACPI Registers - Function 1 AMD Geode™ SC2200 Processor Data Book Reset Value: 0000h...
  • Page 251 Bit 0 of this register must be set to 0 (input) for GPWIO0 to be able to generate an SMI. If enabled, this bit overrides the setting of F1BAR1+I/O Offset 12h[8] and its status is reported in F1BAR0+I/O Offset 00h/ 02h[0]. Reserved. AMD Geode™ SC2200 Processor Data Book GPWIO Control Register 1 (R/W) GPWIO Control Register 2 (R/W) 32580B...
  • Page 252 Second level SMI status is reported at F1BAR0+I/O Offset 20h/22h[2]. Core Logic Module - SMI Status and ACPI Registers - Function 1 GPWIO Data Register (R/W) Reserved ACPI SCI_ROUTING Register (R/W) AMD Geode™ SC2200 Processor Data Book Reset Value: 00h Reset Value: 00h Reset Value: 00000F00h...
  • Page 253 Arbiter Disable. Disables the PCI arbiter when set by the OS. Used during C3 transition. 0: Arbiter not disabled. (Default) 1: Disable arbiter. Offset 21h-FFh The read value for these registers is undefined. AMD Geode™ SC2200 Processor Data Book 0100: IRQ4 1000: IRQ8 0101: IRQ5 1001: IRQ9...

  • Page 254: Table 6-35. F2: Pci Header/Channels 0 And 1 Registers For Ide Controller Configuration

    Reset Value: 00h Reset Value: 00h Reset Value: 00h Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000001h Reset Value: 00h Reset Value: 100Bh Reset Value: 0502h Reset Value: 00h AMD Geode™ SC2200 Processor Data Book...
  • Page 255 Data cycle IDE_IOW# data setup (value + 1 cycle). t2WD. Data cycle IDE_IOW# pulse width minus t3 (value + 1 cycle). t1D. Data cycle address Setup Time (value + 1 cycle). AMD Geode™ SC2200 Processor Data Book Channel 0 Drive 0 PIO Register (R/W) 32580B...
  • Page 256 Core Logic Module - IDE Controller Registers - Function 2 Channel 0 Drive 0 DMA Control Register (R/W) Channel 0 Drive 1 PIO Register (R/W) Channel 0 Drive 1 DMA Control Register (R/W) Reset Value: 00077771h Reset Value: 00009172h Reset Value: 00077771h AMD Geode™ SC2200 Processor Data Book...
  • Page 257 The PIO Mode format is selected in F2 Index 44h[31], bit 31 of this register is defined as reserved. Index 60h-FFh AMD Geode™ SC2200 Processor Data Book Channel 1 Drive 0 PIO Register (R/W) Channel 1 Drive 0 DMA Control Register (R/W)

  • Page 258: Table 6-36. F2Bar4+I/O Offset: Ide Controller Configuration Registers

    Core Logic Module - IDE Controller Registers - Function 2 mats of the I/O mapped IDE Controller Configuration registers that are accessed through F2BAR4. Not Used Not Used AMD Geode™ SC2200 Processor Data Book Reset Value: 00h Reset Value: 00h Reset Value: 00000000h...
  • Page 259 = 1), it loads the pointer and updates this field (by adding 08h) so that is points to the next PRD. When read, this register points to the next PRD. Reserved. Must be set to 0. AMD Geode™ SC2200 Processor Data Book 32580B Not Used...

  • Page 260: Table 6-37. F3: Pci Header Registers For Audio Configuration

    Reset Value: 0280h Reset Value: 00h Reset Value: 040100h Reset Value: 00h Reset Value: 00h Reset Value: 00h Reset Value: 00h Reset Value: 00000000h Reset Value: 00h Reset Value: 100Bh Reset Value: 0503h Reset Value: 00h AMD Geode™ SC2200 Processor Data Book...

  • Page 261: Table 6-38. F3Bar0+Memory Offset: Audio Configuration Registers

    AC97 frame). 0: Not new. 1: New, updated in current frame. AMD Geode™ SC2200 Processor Data Book memory mapped audio configuration registers that are accessed through F3BAR0.
  • Page 262 An SMI is then generated when the End of Page bit is set in the Audio Bus Master 3 SMI Status Register (F3BAR0+Memory Offset 39h[0] = 1). Codec Command Register (R/W) Second Level Audio SMI Status Register (RC) Core Logic Module - Audio Registers - Function 3 Reset Value: 00000000h Reset Value: 0000h AMD Geode™ SC2200 Processor Data Book...
  • Page 263 End of Page bit is set in the SMI Status Register (F3BAR0+Memory Offset 39h[0] = 1). The End of Page bit must be cleared before this bit can be cleared. AMD Geode™ SC2200 Processor Data Book 32580B...
  • Page 264 Second level SMI status is reported at F3BAR0+Memory Offset 10h/12h[0]. Top level is reported at F1BAR0+I/O Offset 00h/02h[1]. SMI generation enabling is at F3BAR0+Memory Offset 18h[2]. Core Logic Module - Audio Registers - Function 3 Reset Value: 00000000h AMD Geode™ SC2200 Processor Data Book...
  • Page 265 Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[1]. Second level SMI status is reported at F3BAR0+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR0+Memory Offset 14h[11]. AMD Geode™ SC2200 Processor Data Book I/O Trap SMI Enable Register (R/W 32580B...
  • Page 266 0: External. 1: Internal. Reserved. Must be set to 0. Core Logic Module - Audio Registers - Function 3 10: I/O Port 260h-26Fh 11: I/O Port 280h-28Fh Internal IRQ Enable Register (R/W) AMD Geode™ SC2200 Processor Data Book Reset Value: 0000h...
  • Page 267 Mask Internal IRQ7. (Write Only) 0: Disable. 1: Enable. Reserved. (Write Only) Must be set to 0. Mask Internal IRQ5. (Write Only) 0: Disable. 1: Enable. AMD Geode™ SC2200 Processor Data Book Internal IRQ Control Register (R/W) 32580B Reset Value: 00000000h...
  • Page 268 0: Disable. 1: Enable. Assert Masked Internal IRQ4. 0: Disable. 1: Enable. Assert Masked Internal IRQ3. 0: Disable. 1: Enable. Reserved. Must be set to 0. Core Logic Module - Audio Registers - Function 3 AMD Geode™ SC2200 Processor Data Book...
  • Page 269 The Physical Region Descriptor (PRD) table consists of one or more entries - each describing a memory region to or from which data is to be transferred. Each entry consists of two DWORDs. DWORD 0: DWORD 1: AMD Geode™ SC2200 Processor Data Book Audio Bus Master 0 Command Register (R/W) Audio Bus Master 0 SMI Status Register (RC) Not Used...
  • Page 270 = Loop Flag (JMP) [28:16] = Reserved (0) [15:0] = Byte Count of the Region (Size) Core Logic Module - Audio Registers - Function 3 Reset Value: 00h Reset Value: 00h Reset Value: 00000000h AMD Geode™ SC2200 Processor Data Book...
  • Page 271 The Physical Region Descriptor (PRD) table consists of one or more entries - each describing a memory region to or from which data is to be transferred. Each entry consists of two DWORDs. DWORD 0: DWORD 1: AMD Geode™ SC2200 Processor Data Book Audio Bus Master 2 Command Register (R/W) Audio Bus Master 2 SMI Status Register (RC) Not Used...
  • Page 272 = Loop Flag (JMP) [28:16] = Reserved (0) [15:0] = Byte Count of the Region (Size) Core Logic Module - Audio Registers - Function 3 Reset Value: 00h Reset Value: 00h Reset Value: 00000000h AMD Geode™ SC2200 Processor Data Book...
  • Page 273 The Physical Region Descriptor (PRD) table consists of one or more entries - each describing a memory region to or from which data is to be transferred. Each entry consists of two DWORDs. DWORD 0: DWORD 1: AMD Geode™ SC2200 Processor Data Book Audio Bus Master 4 Command Register (R/W) Audio Bus Master 4 SMI Status Register (RC) Not Used...
  • Page 274 = Loop Flag (JMP) [28:16] = Reserved (0) [15:0] = Byte Count of the Region (Size) Core Logic Module - Audio Registers - Function 3 Reset Value: 00h Reset Value: 00h Reset Value: 00000000h AMD Geode™ SC2200 Processor Data Book...

  • Page 275: Table 6-39. F5: Pci Header Registers For X-Bus Expansion

    Reserved. Reserved for possible future use by the Core Logic module. Configuration of this register is programmed through the F5BAR1 Mask Register (F5 Index 48h). AMD Geode™ SC2200 Processor Data Book Located in the PCI Header Registers of F5 are six Base...
  • Page 276 Subsystem Vendor ID (RO) Subsystem ID (RO) Reserved F5BAR0 Mask Address Register (R/W) Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00h Reset Value: 100Bh Reset Value: 0505h Reset Value: 00h Reset Value: FFFFFFC1h AMD Geode™ SC2200 Processor Data Book...
  • Page 277 At reset this bit is cleared (0). Writing F5BAR0 sets this bit to 1. If this bit programmed to 0, the decoding of F5BAR0 is dis- abled until either this bit is set to 1 or F5BAR0 is written (which causes this bit to be set to 1). AMD Geode™ SC2200 Processor Data Book F5BAR1 Mask Address Register (R/W)

  • Page 278: Table 6-40. F5Bar0+I/O Offset: X-Bus Expansion Registers

    Core Logic Module - X-Bus Expansion Interface - Function 5 Reserved Reserved trol support registers. Table 6-40 shows the support regis- ters accessed through F5BAR0. I/O Control Register 1 (R/W) AMD Geode™ SC2200 Processor Data Book Reset Value: xxh Reset Value: 00000000h Reset Value: 00000000h Reset Value: 010C0007h...
  • Page 279 0: Disable. 1: Enable. IO_TEST_PORT_REG (Debug Port Pointer). These bits are used to point to the 16-bit slice of the test port bus. AMD Geode™ SC2200 Processor Data Book I/O Control Register 2 (R/W) I/O Control Register 3 (R/W) 32580B...

  • Page 280: Table 6-41. Pciusb: Usb Pci Configuration Registers

    (OHCI) specification. Registers marked as “Reserved”, and reserved bits within a register, should not be changed by software. Vendor Identification Register (RO) Device Identification Register (RO) Command Register (R/W) AMD Geode™ SC2200 Processor Data Book Reset Value: 0E11h Reset Value: A0F8h Reset Value: 00h...
  • Page 281 Index 0Fh This register identifies the control and status of Built-In Self-Test (BIST). The USB does not implement BIST, so this register is read only. AMD Geode™ SC2200 Processor Data Book Status Register (R/W) Device Revision ID Register (RO) PCI Class Code Register (RO)
  • Page 282 Reset Value: 00000000h Reset Value: 00h Reset Value: 0E11h Reset Value: A0F8h Reset Value: 00h Reset Value: 00h Reset Value: 01h Reset Value: 00h Reset Value: 50h Reset Value: 000F0000h Reset Value: 00h Reset Value: 00h AMD Geode™ SC2200 Processor Data Book...

  • Page 283: Table 6-42. Usb_Bar+Memory Offset: Usb Controller Registers

    Offset 0Ch-0Fh Reserved. Read/Write 0s. OwnershipChange. This bit is set when the OwnershipChangeRequest bit of HcCommandStatus is set. 29:7 Reserved. Read/Write 0s. AMD Geode™ SC2200 Processor Data Book HcRevision Register (RO) HcControl Register (R/W) HcCommandStatus Register (R/W) HcInterruptStatus Register (R/W)
  • Page 284 1: Disable interrupt generation due to Ownership Change. 29:7 Reserved. Read/Write 0s. Core Logic Module - USB Controller Registers - PCIUSB HcInterruptEnable Register (R/W) HcInterruptDisable Register (R/W) AMD Geode™ SC2200 Processor Data Book Reset Value = 00000000h Reset Value = 00000000h...
  • Page 285 BulkCurrentED. Pointer to the current Bulk List ED. Reserved. Read/Write 0s. Offset 30h-33h 31:4 DoneHead. Pointer to the current Done List Head ED. Reserved. Read/Write 0s. AMD Geode™ SC2200 Processor Data Book HcHCCA Register (R/W) HcPeriodCurrentED Register (R/W) HcControlHeadED Register (R/W) HcControlCurrentED Register (R/W) HcBulkHeadED Register (R/W)
  • Page 286 HcFrameRemaining Register (RO) HcFmNumber Register (RO) HcPeriodicStart Register (R/W) HcLSThreshold Register (R/W) HcRhDescriptorA Register (R/W) AMD Geode™ SC2200 Processor Data Book Reset Value = 00002EDFh Reset Value = 00000000h Reset Value = 00000000h Reset Value = 00000000h Reset Value = 00000628h...
  • Page 287 Write: ClearGlobalPower. Writing a 1 issues a ClearGlobalPower command to the ports. Writing a 0 has no effect. Note: This register is reset by the UsbReset state. AMD Geode™ SC2200 Processor Data Book HcRhDescriptorB Register (R/W) HcRhStatus Register (R/W) 32580B...
  • Page 288 1: Port is selectively suspended. Write: SetPortSuspend. Writing a 1 sets PortSuspendStatus. Writing a 0 has no effect. Core Logic Module - USB Controller Registers - PCIUSB HcRhPortStatus[1] Register (R/W) AMD Geode™ SC2200 Processor Data Book Reset Value = 00000000h...
  • Page 289 0: Port reset signal is not active. 1: Port reset signal is active. Write: SetPortReset. Writing a 1 sets PortResetStatus. Writing a 0 has no effect. AMD Geode™ SC2200 Processor Data Book HcRhPortStatus[2] Register (R/W) 32580B Reset Value = 00000000h...
  • Page 290 0: Full speed device. 1: Low speed device. Write: ClearPortPower. Writing a 1 clears PortPowerStatus. Writing a 0 has no effect. Core Logic Module - USB Controller Registers - PCIUSB HcRhPortStatus[3] Register (R/W) AMD Geode™ SC2200 Processor Data Book Reset Value = 00000000h...
  • Page 291 HceStatus is 0, IRQ1 is generated: if 1, then an IRQ12 is generated. CharacterPending. When set, an emulation interrupt will be generated when the OutputFull bit of the HceStatus register is set to 0. AMD Geode™ SC2200 Processor Data Book Reserved HceControl Register (R/W)
  • Page 292 This register is the emulation side of the legacy Status register. Core Logic Module - USB Controller Registers - PCIUSB HceInput Register (R/W) HceOutput Register (R/W) HceStatus Register (R/W) AMD Geode™ SC2200 Processor Data Book Reset Value = 000000xxh Reset Value = 000000xxh Reset Value = 00000000h...

  • Page 293: Table 6-43. Dma Channel Control Registers

    Channel 3 Terminal Count. Indicates if TC was reached. 0: No. 1: Yes. AMD Geode™ SC2200 Processor Data Book • DMA Channel Control Registers, see Table 6-43 • DMA Page Registers, see Table 6-44 • Programmable Interval Timer Registers, see Table 6-45 •...
  • Page 294 0: Not masked. 1: Masked. Channel Number Mask Select. 00: Channel 0. 01: Channel 1. 10: Channel 2. 11: Channel 3. Core Logic Module - ISA Legacy Register Space DMA Command Register, Channels 3:0 AMD Geode™ SC2200 Processor Data Book...
  • Page 295 I/O Port 0CCh Not supported. I/O Port 0CEh Not supported. AMD Geode™ SC2200 Processor Data Book DMA Channel 4 Address Register (R/W) DMA Channel 4 Transfer Count Register (R/W) DMA Channel 5 Address Register (R/W) DMA Channel 5 Transfer Count Register (R/W)
  • Page 296 0: Normal. 1: Compressed. Channels 7:4. 0: Disable. 1: Enable. Reserved. Must be set to 0. Core Logic Module - ISA Legacy Register Space DMA Status Register, Channels 7:4 DMA Command Register, Channels 7:4 AMD Geode™ SC2200 Processor Data Book...
  • Page 297 DMA Master Clear Command, Channels 7:4 (W) Note: Channels 5, 6, and 7 are not supported. I/O Port 0DCh DMA Clear Mask Register Command, Channels 7:4 (W) Note: Channels 5, 6, and 7 are not supported. AMD Geode™ SC2200 Processor Data Book 32580B...
  • Page 298 DMA Channel 1 High Page Register (R/W) DMA Channel 0 High Page Register (R/W) DMA Channel 6 High Page Register (R/W) DMA Channel 7 High Page Register (R/W) DMA Channel 5 High Page Register (R/W) AMD Geode™ SC2200 Processor Data Book...

  • Page 299: Table 6-45. Programmable Interval Timer Registers

    11: R/W LSB, followed by MSB. Current Counter Mode. 0-5. BCD Mode. 0: Binary. 1: BCD (Binary Coded Decimal). AMD Geode™ SC2200 Processor Data Book PIT Timer 0 Counter PIT Timer 0 Status PIT Timer 1 Counter (Refresh) PIT Timer 1 Status (Refresh)
  • Page 300 Current Counter Mode. 0-5. BCD Mode. 0: Binary. 1: BCD (Binary Coded Decimal). Core Logic Module - ISA Legacy Register Space PIT Timer 2 Counter (Speaker) PIT Timer 2 Status (Speaker) PIT Mode Control Word Register AMD Geode™ SC2200 Processor Data Book...

  • Page 301: Table 6-46. Programmable Interrupt Controller Registers

    IRQ4 / IRQ12 Mask. 0: Not Masked. 1: Mask. IRQ3 / IRQ11 Mask. 0: Not Masked. 1: Mask. AMD Geode™ SC2200 Processor Data Book Master / Slave PIC ICW1 (WO) Master / Slave PIC OCW1 (except immediately after ICW1 is written) 32580B...
  • Page 302 100: Set rotate in Auto EOI mode 101: Rotate on non-specific EOI command 110: Set priority command (bits [2:0] must be valid) 111: Rotate on specific EOI command Master / Slave PIC OCW3 (WO) for OCW3 Commands (RO) AMD Geode™ SC2200 Processor Data Book...
  • Page 303 1: Yes. IRQ3 / IRQ11 In-Service. 0: No. 1: Yes. IRQ2 / IRQ10 In-Service. 0: No. 1: Yes. IRQ1 / IRQ9 In-Service. 0: No. 1: Yes. IRQ0 / IRQ8 In-Service. 0: No. 1: Yes. AMD Geode™ SC2200 Processor Data Book 32580B...

  • Page 304: Table 6-47. Keyboard Controller Registers

    This bit must be cleared before the generation of another reset. Core Logic Module - ISA Legacy Register Space Port B Control Register (R/W) Port A Control Register (R/W) AMD Geode™ SC2200 Processor Data Book Reset Value: 00x01100b Reset Value: 02h...

  • Page 305: Table 6-48. Real-Time Clock Registers

    1: Level. IRQ4 Edge or Level Sensitive Select. Selects PIC IRQ4 sensitivity configuration. 0: Edge. 1: Level. AMD Geode™ SC2200 Processor Data Book Table 6-48. Real-Time Clock Registers RTC Address Register (WO) RTC Data Register (R/W) RTC Extended Address Register (WO) RTC Data Register (R/W) Table 6-49.
  • Page 306 IRQ9 Edge or Level Sensitive Select. Selects PIC IRQ9 sensitivity configuration. 0: Edge. 1: Level. Reserved. Must be set to 0. Interrupt Edge/Level Select Register 2 (R/W) Core Logic Module - ISA Legacy Register Space Reset Value: 00h AMD Geode™ SC2200 Processor Data Book...

  • Page 307: 7.0Video Processor Module

    • Overlay of video up to 16 bpp • Supports chroma key and color key for both graphics and video streams AMD Geode™ SC2200 Processor Data Book 7.0Video Processor Module • Supports alpha-blending with up to three alpha windows that can overlap one another •...

  • Page 308: Module Architecture

    The following subsections describe each block in detail. Video Formatter Horizontal Downscaler, Video Line Buffer, Horizontal Data Video and Vertical Upscalers, and Filters Mixer/Blender Overlay with Gamma RAM and Alpha Blending AMD Geode™ SC2200 Processor Data Book Video Processor Module TFT_IF CRT_IF DACs...

  • Page 309: Functional Description

    This method is known as Capture Video mode. How each mode is setup and operates is explained further in Section 7.2.1 on page 323. AMD Geode™ SC2200 Processor Data Book 32580B VBI Support VBI (vertical blanking interval) data is placed in the video data stream during a portion of the vertical retrace period.

  • Page 310: Figure 7-2. Ntsc 525 Lines, 60 Hz, Odd Field

    Active Video Logical Line 24 — Scan Lines 287-525 Vertical Retrace - Logical Line 24 — Scan Line 264 (Not normally User Data) Video Processor Module VSYNC Start VSYNC End VSYNC Start VSYNC End AMD Geode™ SC2200 Processor Data Book...

  • Page 311: Figure 7-4. Vip Block Diagram

    Data CCIR-656 Decoder Clock Direct Video/VBI AMD Geode™ SC2200 Processor Data Book Video data is clocked out using the GX1’s Video port clock (75, 116, or 133 MHz GX1 core clock divided by 2 or 4). 7.2.1.1 Direct Video Mode...
  • Page 312 The new address will not take affect until the start of a new display con- troller frame. The field that was just received can be known reading Current F4BAR2+Memory Offset 08h[24]. AMD Geode™ SC2200 Processor Data Book Field...

  • Page 313: Figure 7-5. Capture Video Mode Bob Example Using One Video Frame Buffer

    Weave method. Since at least double buffering is required, more of the VIP’s control registers are used for Weave than required for Bob during video runtime. AMD Geode™ SC2200 Processor Data Book Video Data Even Base (F4BAR2+Memory Offset 24h) Address not changed during runtime...

  • Page 314: Figure 7-6. Capture Video Mode Weave Example Using Two Video Frame Buffers

    Video Frame Buffer #2 Line 1 Odd Field Line 1 Even Field Line 2 Odd Field Line 2 Even Field Line n-1 Odd Field Line n-1 Even Field Line n Odd Field Line n Even Field AMD Geode™ SC2200 Processor Data Book...

  • Page 315: Figure 7-7. Video Block Diagram

    Video Module 4-Tap Horizontal Video Input Downscaler Formatter AMD Geode™ SC2200 Processor Data Book RGB 5:6:5 – For this format each pixel is described as a 16-bit value: Bits [15:11] = Red Bits [10:5] = Green Bits [4:0] = Blue YUV 4:2:0 –...

  • Page 316: Figure 7-8. Horizontal Downscaler Block Diagram

    (F4BAR0+Memory Offset 3Ch) selects the type of down- scaling factor to be used. Note: There is no vertical downscaling in the Video Pro- cessor. Bypass 4-Tap Horizontal Filtering Downscaler Downscale Factors Video Processor Module Video Downscaler Control To Line Buffers AMD Geode™ SC2200 Processor Data Book register...

  • Page 317: Figure 7-9. Linear Interpolation Calculation

    YUV 4:4:4 format. RGB data is not translated. There is no direct program control of the Formatter. i+1,j Figure 7-9. Linear Interpolation Calculation AMD Geode™ SC2200 Processor Data Book 7.2.2.5 2-Tap Vertical and Horizontal Upscalers After the video data has been buffered, the upscaling algo- rithm can be applied.

  • Page 318: Figure 7-10. Mixer/Blender Block Diagram

    GV_GAMMA_SEL * /GAMMA_EN Optional Gamma Correction Color/Chroma 1/2 Y Mixer/Blender Flicker Filter RGB to Cursor Color Key Compare Compare Color/Chroma Key Video Processor Module CRT DACs and TFT Interface Key and YUV Data TVOUT Block AMD Geode™ SC2200 Processor Data Book...

  • Page 319: Table 7-1. Valid Mixing/Blending Configurations

    01h. The address 01h would contain the data 02h and so on. This would have the effect of increasing each original Red, Green, and Blue value by one. AMD Geode™ SC2200 Processor Data Book Mode Comment Input: YUV Progressive Video •...

  • Page 320: Figure 7-11. Graphics/Video Frame With Alpha Windows

    Offset 60h-88h. Graphics Window (GFX_INS_VIDEO = 0) Video Window Video X Position Register Alpha Window #1 Alpha Window 3 X Position Register Alpha Window #3 Video Processor Module Alpha Window 3 Y Position Register AMD Geode™ SC2200 Processor Data Book...

  • Page 321: Table 7-2. Truth Table For Alpha Blending

    ALPHAx_COLOR_REG_EN = 1 = 1) Window x ALPHAx_COLOR_REG_EN = 0 COLOR_CHROMA_SEL: F4BAR0+Memory Offset 04h[20]. GFX_INS_VIDEO: F4BAR0+Memory Offset 4Ch[8]. ALPHAx_COLOR_REG_EN: F4BAR0+Memory Offsets 68h[24], 78h[24], and 88h[24]. AMD Geode™ SC2200 Processor Data Book Graphics Data Match Cursor Configuration Color Key GFX_INS_VIDEO = 0...

  • Page 322: Figure 7-12. Color Key And Alpha Blending Logic

    Pixel value matches normal color COLOR_CHROMA _SEL = 1 window Use graphics value for this pixel Video Processor Module COLOR_CHROMA _SEL = 1 Use video value Use graphics for this pixel value for this pixel AMD Geode™ SC2200 Processor Data Book...

  • Page 323: Figure 7-13. Dac Voltage Levels

    Each integrated DAC is an 8-bit current output type which can run at a clock rate of up to 135 MHz. The integrated AMD Geode™ SC2200 Processor Data Book DAC can generate voltage levels from 0 to 1.0V, when driv- ing 75Ω...

  • Page 324: Figure 7-14. Tft Power Sequence

    PWR_SEQ_DLY (bits [19:17]) When FP_PWR_EN (bit 6) is set to 0, the reverse sequence happens for powering down the TFT. is time to next VSYNC is a programmable multiple of frame time Figure 7-14. TFT Power Sequence Video Processor Module AMD Geode™ SC2200 Processor Data Book...

  • Page 325: Figure 7-15. Pll Block Diagram

    = (m + 1) / (n+ 1) x F Compare Divider AMD Geode™ SC2200 Processor Data Book The integrated PLL can generate any frequency by writing into the CRT-m and CRT-n bit fields (FBAR0+Memory Off- set 2Ch). Additionally, 16 preprogrammed VGA frequencies...

  • Page 326: Register Descriptions

    0504h Reset Value 00000000h x0000000h 00000000h 00000000h 00000000h 00000000h 00000000h xxxxxxxxh xxxxxxxxh AMD Geode™ SC2200 Processor Data Book Reference (Table 7-6) Page 341 Page 341 Page 341 Page 341 Page 341 Page 341 Page 341 Page 341 Page 341 Page 341...
  • Page 327 Video Processor Test Mode Register 40Ch-41Fh Reserved 420h-423h GenLock Register 424h-427h GenLock Delay Register 428h-43Bh Reserved 43Ch-43Fh Continuous GenLock Time-out Register AMD Geode™ SC2200 Processor Data Book 32580B Reset Reference Value (Table 7-7) 00001400h Page 348 00000000h Page 348 00000000h...

  • Page 328: Table 7-5. F4Bar2: Vip Support Registers Summary

    Page 362 xxxxxxxxh Page 362 00000000h Page 362 00000000h Page 362 00000000h Page 363 00000000h Page 363 00000000h Page 363 00000000h Page 363 00000000h Page 363 00000000h Page 363 00000000h Page 364 00000000h Page 364 AMD Geode™ SC2200 Processor Data Book...

  • Page 329: Table 7-6. F4: Pci Header Registers For Video Processor Support Registers

    This register identifies the system interrupt controllers to which the device’s interrupt pin is connected. The value of this register is used by device drivers and has no direct meaning to this function. AMD Geode™ SC2200 Processor Data Book Located in the PCI Header Registers of F4 are three Base Address Registers (F4BARx) used for pointing to the regis- ter spaces designated for Video Processor support.
  • Page 330 This register selects which interrupt pin the device uses. VIP uses INTC# after reset. INTA#, INTB# or INTD# can be selected by writing 1, 2 or 4, respectively. Index 3Eh-FFh Video Processor Module - Video Processor Registers - Function 4 Interrupt Pin Register (R/W) Reserved AMD Geode™ SC2200 Processor Data Book Reset Value: 03h Reset Value: 00h...

  • Page 331: Table 7-7. F4Bar0+Memory Offset: Video Processor Configuration Registers

    U and V data for that same line. Reserved. AMD Geode™ SC2200 Processor Data Book Note: Reserved bits that are not defined as “must be set to 0 or 1" should be written with a value that is read from them.
  • Page 332 Video Processor Module - Video Processor Registers - Function 4 Display Configuration Register (R/W) 100: Baseline, sync not moved 101: Sync moved 1 clock forward 110: Sync moved 2 clocks forward 111: Sync moved 3 clocks forward Reset Value: x0000000h AMD Geode™ SC2200 Processor Data Book...
  • Page 333 VID_Y_END (Video Y End Position). Represents the vertical end position of the video window (not inclusive). This value is calculated according to the following formula: Value = Desired screen position + (V_TOTAL – V_SYNC_END) + 2. 15:11 Reserved AMD Geode™ SC2200 Processor Data Book Video X Position Register (R/W) Video Y Position Register (R/W) 32580B Reset Value: 00000000h...
  • Page 334 Video Processor Module - Video Processor Registers - Function 4 Video Upscale Register (R/W) Video Color Key Register (R/W) Video Color Mask Register (R/W) AMD Geode™ SC2200 Processor Data Book Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h...
  • Page 335 SEL_REG_CAL. Selects specific or previously-calculated values. 0: Values previously calculated from the CLK_SEL bits (bits [19:16]). 1: Values according to the m (bits [14:8]), n (bits [3:0]), and CLK_DIV_SEL (bits [22:21]) fields. AMD Geode™ SC2200 Processor Data Book Reserved Miscellaneous Register (R/W)
  • Page 336 1110: 27 1011: 94.5 1111: 24.923052 Reserved Reserved Reserved Video Downscaler Control Register (R/W) Video Downscaler Coefficient Register (R/W) Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h AMD Geode™ SC2200 Processor Data Book...
  • Page 337 10: Highest priority. 11: Illegal. Note: Priority of enabled alpha windows must be different. 15:14 Reserved. AMD Geode™ SC2200 Processor Data Book CRC Signature Register (R/W) Device and Revision Identification (RO) 32580B Reset Value: xxxxx100h Reset Value: 0000xxxxh Reset Value: 00060000h...
  • Page 338 Video Processor Module - Video Processor Registers - Function 4 Cursor Color Key Register (R/W) AMD Geode™ SC2200 Processor Data Book Reset Value: 00000000h...
  • Page 339 Value = Desired screen position + (V_TOTAL – V_SYNC_END) + 1. Offset 68h-6Bh 31:25 Reserved. AMD Geode™ SC2200 Processor Data Book Cursor Color Mask Register (R/W) Cursor Color Register 1 (R/W) Cursor Color Register 2 (R/W) Alpha Window 1 X Position Register (R/W)
  • Page 340 Alpha Window 1 Control Register (R/W) Alpha Window 2 X Position Register (R/W) Alpha Window 2 Y Position Register (R/W) Alpha Window 2 Color Register (R/W) Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h AMD Geode™ SC2200 Processor Data Book...
  • Page 341 Value = Desired screen position + (V_TOTAL – V_SYNC_END) + 1. Offset 88h-8Bh 31:25 Reserved. AMD Geode™ SC2200 Processor Data Book Alpha Window 2 Control Register (R/W) Alpha Window 3 X Position Register (R/W) Alpha Window 3 Y Position Register (R/W)
  • Page 342 Video Processor Module - Video Processor Registers - Function 4 Alpha Window 3 Control Register (R/W) Video Request Register (R/W) Alpha Watch Register (RO) Reserved Video Processor Display Mode Register (R/W) Reset Value: 00000000h Reset Value: 001B0017h Reset Value: 00000000h Reset Value: 00000000h AMD Geode™ SC2200 Processor Data Book...
  • Page 343 20:0 GENLOCK_DEL (GenLock Delay). Indicates the delay (in 27 MHz clocks) between the VIP VSYNC and the GX1 module’s Display Controller VSYNC. Offset 428h-43Bh AMD Geode™ SC2200 Processor Data Book Reserved Video Processor Test Mode Register (R/W) Reserved GenLock Register (R/W)
  • Page 344 Table 7-7. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued) Description Offset 43Ch-43Fh Continuous GenLock Timeout Register (R/W) Reset Value: 1FFF1FFFh 31:16 CGENTO1 (Even Field Continuous GenLock Timeout). 15:0 CGENTO0 (Odd Field Continuous GenLock Timeout). AMD Geode™ SC2200 Processor Data Book...

  • Page 345: Table 7-8. F4Bar2+Memory Offset: Vip Configuration Registers

    Interrupt generation can be enabled regardless of whether or not video capture (store to memory) is enabled. 0: Disable. 1: Enable. 15:11 Reserved. Must be set to 0. AMD Geode™ SC2200 Processor Data Book are located. Table 7-8 shows the memory mapped VIP sup- port registers accessed through F4BAR2. Video Interface Control Register (R/W) 32580B...
  • Page 346 0: VBI data is not being stored to memory. 1: VBI data is now being stored to memory. Video Processor Module - Video Processor Registers - Function 4 Video Interface Status Register (R/W) Reset Value: xxxxxxxxh AMD Geode™ SC2200 Processor Data Book...
  • Page 347 31:16 Reserved. 15:0 Video Data Pitch. Specifies the logical width of the video data buffer. Bits [1:0] are always 0. Offset 2Ch-3Fh AMD Geode™ SC2200 Processor Data Book Reserved Video Current Line Register (RO) Video Line Target Register (R/W) Reserved...
  • Page 348 Video Processor Module - Video Processor Registers - Function 4 VBI Data Odd Base Register (R/W) VBI Data Even Base Register (R/W) VBI Data Pitch Register (R/W) Reserved AMD Geode™ SC2200 Processor Data Book Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00h...

  • Page 349: 8.0Debugging And Monitoring

    EXTEST SAMPLE/PRELOAD IDCODE CLAMP Reserved Reserved BYPASS AMD Geode™ SC2200 Processor Data Book 8.0Debugging and Monitoring 8.1.2 Optional Instruction Support The TAP supports the following IEEE optional instructions: • IDCODE Presents the contents of the Device Identification register in serial format.
  • Page 350 32580B Debugging and Monitoring AMD Geode™ SC2200 Processor Data Book...

  • Page 351: 9.0Electrical Specifications

    Note 2. No bias. Note 3. Voltage min is -0.8V with a transient voltage of 20 ns or less. Note 4. Voltage max is 4.0V with a transient voltage of 20 ns or less. AMD Geode™ SC2200 Processor Data Book 9.0Electrical Specifications 9.1.2...

  • Page 352: Table 9-3. Operating Conditions

    2.21 3.46 3.46 requires a 0.1 µF bypass capac- 1.89 2.21 1.89 2.21 (Output Low Current) op- and V be less than 0.25V, in order CORE be less than 0.25V, in order to reduce AMD Geode™ SC2200 Processor Data Book...

  • Page 353: Table 9-4. Power Planes Of External Interface Signals

    • Sleep (SL2): This is the lowest power state the SC2200 can be in with voltage still applied to the device’s core and I/O supply pins. This is equivalent to the ACPI spec- ification’s “S1” state. AMD Geode™ SC2200 Processor Data Book 32580B Balls CCCRT CCUSB 9.1.5.2...

  • Page 354: Table 9-5. System Conditions Used To Measure Sc2200 Current During The On State

    Typ Avg Abs Max = 3.3V = 3.3V = 3.3V CORE 1090 CORE 1100 1400 CORE AMD Geode™ SC2200 Processor Data Book Electrical Specifications SDRAM DCLK Frequency Frequency 50 MHz (Note 2) Nominal 135 MHz (Note 3) Unit Comments for V...

  • Page 355: Table 9-7. Dc Characteristics For Active Idle, Sleep, And Off States

    Note 4. Applies to SC2200UFH-233B, SC2200UFH-233BF, SC2200UFH-266B, and SC2200UFH-266BF. Non-B suffix parts have a maximum I current of 50 µA (see Section A.1 "Order Information" on page 447). AMD Geode™ SC2200 Processor Data Book Typ Avg Abs Max = 3.3V = 3.3V...

  • Page 356: Table 9-8. Ball Capacitance And Inductance

    Output Pin Capacitance Pin Inductance Note 1. T = 25°C, f = 1 MHz. All capacitances are not 100% tested. Note 2. Not 100% tested. Unit AMD Geode™ SC2200 Processor Data Book Electrical Specifications Comment Note 1 Note 1 Note 1...

  • Page 357: Pull-Up And Pull-Down Resistors

    PUNote 2 PDNote 2 SLIN#/ASTRB# STB#/WRITE# INIT# JTAG AMD Geode™ SC2200 Processor Data Book Note: The resistors described in this table are imple- mented as transistors. The resistance for PUs assumes V Table 9-9. Balls with PU/PD Resistors Typ (Note 1) Value [Ω]...

  • Page 358: Dc Characteristics

    ) with weak pull-down Electrical Specifications Reference Section 9.2.1 Section 9.2.2 Section 9.2.3 Section 9.2.4 Section 9.2.5 Section 9.2.6 Section 9.2.7 Section 9.2.8 Section 9.2.9 Section 9.2.10 Section 9.2.11 Section 9.2.12 Section 9.2.13 Section 9.2.14 Section 9.2.15 AMD Geode™ SC2200 Processor Data Book...
  • Page 359 Note 3. Input leakage currents include HIZ output leakage for all bidirectional buffers with TRI-STATE outputs. Note 4. See Exceptions 2 and 3 in Section 9.2.15.1 on page 383. AMD Geode™ SC2200 Processor Data Book Unit -0.5 (Note 1) µA...
  • Page 360 (Note 1) µA −10 µA Unit +0.3 (Note 1) -0.5 (Note 1) µA µA Unit 0.5V +0.3 (Note 1) -0.5 0.3V (Note 1) µA µA AMD Geode™ SC2200 Processor Data Book Electrical Specifications Comments During Reset: V Comments Comments Comments...

  • Page 361: Figure 9-1. Differential Input Sensitivity For Common Mode Range

    DC Characteristics AC97 Symbol Parameter Output High Voltage Output Low Voltage 9.2.10 DC Characteristics Symbol Parameter Output Low Voltage AMD Geode™ SC2200 Processor Data Book +0.3 (Note 1) -0.5 (Note 1) Common Mode Input Voltage (volts) 0.9V 0.1V 32580B Unit Comments µA...
  • Page 362 ⎝ R pull up – V IN V SS – ⎛ ----------------------------------------- - ⎝ R pull down AMD Geode™ SC2200 Processor Data Book Electrical Specifications Comments = 1500 μA Comments = -p mA = n mA Comments = -500 μA =1500 μA...

  • Page 363: Ac Characteristics

    B = Minimum Output or Float Delay Specification C = Minimum Input Setup Specification D = Minimum Input Hold Specification Figure 9-2. General Drive level and Measurement Points AMD Geode™ SC2200 Processor Data Book Table 9-11. Default Levels for Measurement of Switching Parameters Symbol...

  • Page 364: Memory Controller Interface

    SDCLK_IN INPUTS Legend: A = Maximum Output Delay B = Minimum Output Delay C = Minimum Input Setup D = Minimum Input Hold Figure 9-3. Drive Level and Measurement Points Valid Output Electrical Specifications AMD Geode™ SC2200 Processor Data Book...
  • Page 365 For example, for a 266 MHz SC2200 running a 88.7 MHz SDRAM clock, with a shift value of 3: t1 Min = -3 + (3 * (3.76 * 0.45)) = 2.08 ns t1 Max = 0.1 + (3 * (3.76 * 0.45)) = 5.18 ns AMD Geode™ SC2200 Processor Data Book 32580B Unit -3.0 + (x...

  • Page 366: Figure 9-4. Memory Controller Output Valid Timing Diagram

    Control Output, MA[12:0] BA[1:0], MD[63:0] Figure 9-4. Memory Controller Output Valid Timing Diagram SDCLK_IN MD[63:0] Data Valid Read Data In Figure 9-5. Read Data In Setup and Hold Timing Diagram Electrical Specifications Data Valid AMD Geode™ SC2200 Processor Data Book...

  • Page 367: Figure 9-6. Video Input Port Timing Diagram

    VPCKIN fall/rise time VPCK_FR VPCKIN duty cycle VPCK_D Note 1. Guaranteed by characterization. VPCKIN PCK_FR VPD[7:0] Figure 9-6. Video Input Port Timing Diagram AMD Geode™ SC2200 Processor Data Book 32580B 35/65 VP_C PCK_FR VP_S VP_H Unit Comments Note 1...

  • Page 368: Figure 9-7. Tft Timing Diagram

    Note that signals DDC_SCL and DDC_SDA of the CRT interface are compliant with standard ACCESS.bus timing and are controlled by software. Table 9-14. TFT Timing Parameters 12.5 CLK_P Figure 9-7. TFT Timing Diagram Electrical Specifications Unit Comments Note 1 40/60 CLK_RF AMD Geode™ SC2200 Processor Data Book...
  • Page 369 Note 6. AV changes within the range of 3V to 3.6V. Output voltage is measured for peak-to-peak maximum change. CCRT PSSR is the ratio of the measurement of output at AV AMD Geode™ SC2200 Processor Data Book 32580B Unit Comments 0.72...
  • Page 370 - 1 μs - 1 μs SCLhigho SCLhigho SCLhigho SCLhigho SCLhigho SDAro SCLhigho SDAfo AMD Geode™ SC2200 Processor Data Book Electrical Specifications Unit Comments Before Stop condition After Start condition Before Start condition Before AB1C/AB2C rising edge Before AB1C/AB2C rising edge μs...

  • Page 371: Figure 9-8. Acb Signals: Rising Time And Falling Timing Diagram

    Figure 9-8. ACB Signals: Rising Time and Falling Timing Diagram AB1D AB2D DLCs DLCo AB1C AB2C Figure 9-9. ACB Start and Stop Condition Timing Diagram AMD Geode™ SC2200 Processor Data Book SCLfo 0.7V 0.3V SDAr 0.7V 0.3V SCLr Stop Condition...

  • Page 372: Figure 9-10. Acb Start Condition Timing Diagram

    Figure 9-10. ACB Start Condition Timing Diagram AB1D AB2D AB1C AB2C SDAvo SDAho Figure 9-11. ACB Data Bit Timing Diagram Start Condition DHCsi CSTRsi CSTRhi DHCso CSTRso CSTRho SDAsi SDAso SCLlowi SCLlowo AMD Geode™ SC2200 Processor Data Book Electrical Specifications SDAhi SDAho SCLhighi SCLhigho...

  • Page 373: Pci Bus Interface

    Output Buffer Figure 9-12. Testing Setup for Slew Rate and Minimum Timing AMD Geode™ SC2200 Processor Data Book All parameters in Table 9-23 are not 100% tested. The parameters in this table are further described in Figure 9- Table 9-18. PCI AC Specifications -12V -17.1(V...

  • Page 374: Figure 9-13. V/I Curves For Pci Output Signals

    >V >0.7V Figure 9-13. V/I Curves for PCI Output Signals Output Voltage Volts Test Point Drive Point Drive Point -48V +0.4V = (256/V Electrical Specifications Pull-Down 0.5V Test Point Equation B for 0V<V <0.18V AMD Geode™ SC2200 Processor Data Book...

  • Page 375: Figure 9-14. Pciclk Timing And Measurement Points

    Note 4. The minimum PCIRST# slew rate applies only to the rising (de-assertion) edge of the reset signal. See Figure 9-18 for PCIRST# timing. 0.5 V 0.4 V PCICLK 0.3 V Figure 9-14. PCICLK Timing and Measurement Points AMD Geode™ SC2200 Processor Data Book Table 9-19. PCI Clock Parameters 0.6V 0.2V HIGH 32580B Unit...

  • Page 376: Figure 9-15. Load Circuits For Maximum Time Measurements

    Note 1, Note 3, Note 1, Note 3, Note 4 Note 4 Note 4 Note 3, Note 5 µs Note 3, Note 5 Note 3, Note 5, Note 6 (Max) Falling Edge 0.5" max. Ω 10 pF AMD Geode™ SC2200 Processor Data Book...

  • Page 377: Figure 9-16. Output Timing Measurement Conditions

    Note 2. V specifies the maximum peak-to-peak waveform allowed for measuring input timing. PCICLK Output Delay TRI-STATE Output Figure 9-16. Output Timing Measurement Conditions AMD Geode™ SC2200 Processor Data Book Value Unit 0.6 V 0.2 V 0.4 V 0.285 V 0.615 V 0.4 V...

  • Page 378: Figure 9-17. Input Timing Measurement Conditions

    Note: The value of t is 500 ns (maximum) from the power rail which exceeds specified tolerance by more than FAIL 500 mV. TEST Input Valid TEST RST-CLK Figure 9-18. PCI Reset Timing Electrical Specifications TEST FAIL RST-OFF AMD Geode™ SC2200 Processor Data Book...
  • Page 379 MEMW#/WR#/DOCW# Hold after IOCHRDY RE IOCHRDY valid after IOR#/MEMR#/ RDYA1 RD#/DOCR#/IOW#/MEMW#/WR#/ DOCW# FE AMD Geode™ SC2200 Processor Data Book The ISA Clock divisor (defined in F0 Index 50h[2:0] of the Core Logic module) is 011. Table 9-22. Sub-ISA Timing Parameters Width (Bits)
  • Page 380 8, 16 M, I/O 8, 16 8, 16 M, I/O 8, 16 M, I/O 8, 16 M, I/O 8, 16 M, I/O AMD Geode™ SC2200 Processor Data Book Electrical Specifications Figure Comments 9-19 9-20 9-19 9-20 9-19 9-20 9-19 9-19...

  • Page 381: Figure 9-19. Sub-Isa Read Operation Timing Diagram

    MEMW#/DOCW# D[15:0] (Read) D[15:0] (Write) IOCHRDY RDYAx Note: x indicates a numeric index for the relevant symbol. Figure 9-19. Sub-ISA Read Operation Timing Diagram AMD Geode™ SC2200 Processor Data Book IOCSA IOCSH Valid RVDS Valid Data RDYH 32580B Valid RCUx...

  • Page 382: Figure 9-20. Sub-Isa Write Operation Timing Diagram

    MEMW#/DOCW# TRDE# D[15:0] IOCHRDY IOR#/RD# MEMR#/DOCR# Note: x indicates a numeric index for the relevant symbol. Figure 9-20. Sub-ISA Write Operation Timing Diagram IOCSA Valid Valid Data RDYAx RDYH Electrical Specifications IOCSH Valid WCUx AMD Geode™ SC2200 Processor Data Book...

  • Page 383: Figure 9-21. Lpc Output Timing Diagram

    Input Hold time PCICLK LPC Signals/ SERIRQ Figure 9-21. LPC Output Timing Diagram PCICLK LPC Signals/ SERIRQ AMD Geode™ SC2200 Processor Data Book Unit Input Valid Figure 9-22. LPC Input Timing Diagram 32580B Comments After PCICLK rising edge After PCICLK rising edge...

  • Page 384: Ide Interface

    IDE signals rise time (from 0.1V IDE_RISE IDE_RST# pulse width IDE_RST_PW IDE_RST# to 0.1V to 0.9V IDE_RST_PW Figure 9-23. IDE Reset Timing Diagram Electrical Specifications Unit Comments = 40 pF = 40 pF µs AMD Geode™ SC2200 Processor Data Book...
  • Page 385 If the device is not driving IDE_IORDY[0:1] negated after activation (t is met and t is not applicable. If the device is driving IDE_IORDY[0:1] negated after activation (t IDE_IOR[0:1]# or IDE_IOW[0:1]#, then t AMD Geode™ SC2200 Processor Data Book Mode 1250 1250...

  • Page 386: Figure 9-24. Register Transfer To/From Device Timing Diagram

    IDE_IOR[0:1]# or IDE_IOW[0:1]#. but causes IDE_IORDY[0:1] to be asserted before t . IDE_IORDY[0:1] is released prior to negation and may be asserted for no before asserting IDE_IORDY[0:1]. Electrical Specifications . IDE_IORDY[0:1] is AMD Geode™ SC2200 Processor Data Book...
  • Page 387 If the device is not driving IDE_IORDY[0:1] negated after the activation (t then t is met and t is not applicable. If the device is driving IDE_IORDY[0:1] negated after the activation (t IDE_IOR[0:1]# or IDE_IOW[0:1]#, then t AMD Geode™ SC2200 Processor Data Book Mode 1250 1250 1250...

  • Page 388: Figure 9-25. Pio Data Transfer To/From Device Timing Diagram

    IDE_IOR[0:1]# or IDE_IOW[0:1]#. but causes IDE_IORDY[0:1] to be asserted before t . IDE_IORDY[0:1] is released prior to negation and may be asserted for no before asserting IDE_IORDY[0:1]. Electrical Specifications . IDE_IORDY[0:1] is AMD Geode™ SC2200 Processor Data Book...
  • Page 389 KR/KW data.) AMD Geode™ SC2200 Processor Data Book Mode is the minimum command active time, and t and t and t . (This means that a host implementation can lengthen t KR/KW is equal to or greater than the value reported in the device’s IDENTIFY DEVICE...

  • Page 390: Figure 9-26. Multiword Dma Data Transfer Timing Diagram

    IDE_DREQ[0:1] asserted and wait for the host to reasse IDE_DACK[0:1]#. This signal can be negated by the host to Suspend the DMA transfer in process. Figure 9-26. Multiword DMA Data Transfer Timing Diagram Electrical Specifications AMD Geode™ SC2200 Processor Data Book...
  • Page 391 (either sender or recipient) is wait- ing for the other agent to respond with a signal before proceeding. t is a limited timeout with a defined minimum. t AMD Geode™ SC2200 Processor Data Book Mode 0 Mode 1 is an unlimited interlock with no maximum time value.

  • Page 392: Figure 9-27. Initiating An Ultradma Data In Burst Timing Diagram

    (DSTROBE[0:1]) signal lines are not in effect until IDE_REQ[0:1] and IDE_DACK[0:1]# are asserted. Figure 9-27. Initiating an UltraDMA Data in Burst Timing Diagram after the negation of DMARDY. Both STROBE and DMARDY timing measurements ZIORDY Electrical Specifications AMD Geode™ SC2200 Processor Data Book...

  • Page 393: Figure 9-28. Sustained Ultradma Data In Burst Timing Diagram

    Figure 9-28. Sustained UltraDMA Data In Burst Timing Diagram AMD Geode™ SC2200 Processor Data Book 2CYC 2CYC...

  • Page 394: Figure 9-29. Host Pausing An Ultradma Data In Burst Timing Diagram

    IDE_IOR[0:1]# (HDMARDY[0:1]#) is de-asserted. If the t timing is not satisfied, the host may receive up to two additional data WORDs from the device. Figure 9-29. Host Pausing an UltraDMA Data In Burst Timing Diagram Electrical Specifications AMD Geode™ SC2200 Processor Data Book...

  • Page 395: Figure 9-30. Device Terminating An Ultradma Data In Burst Timing Diagram

    Note: The definitions for the IDE_IOW[0:1]# (STOP[0:1]#), IDE_IOR[0:1]# (HDMARDY[0:1]#), and IDE_IRDY[0:1] (DSTROBE[0:1]) signal lines are no longer in effect after IDE_DREQ[0:1] and IDE_DACK[0:1]# are de-asserted. Figure 9-30. Device Terminating an UltraDMA Data In Burst Timing Diagram AMD Geode™ SC2200 Processor Data Book 32580B IORDZ...

  • Page 396: Figure 9-31. Host Terminating An Ultradma Data In Burst Timing Diagram

    Note: The definitions for the IDE_IOW[0:1]# (STOP[0:1]#), IDE_IOR[0:1]# (HDMARDY[0:1]#), and IDE_IRDY[0:1] (DSTROBE[0:1]) signal lines are no longer in effect after IDE_DREQ[0:1] and IDE_DACK[0:1] are de-asserted. Figure 9-31. Host Terminating an UltraDMA Data In Burst Timing Diagram IORDYZ AMD Geode™ SC2200 Processor Data Book Electrical Specifications...

  • Page 397: Figure 9-32. Initiating An Ultradma Data Out Burst Timing Diagram

    Note: The definitions for the IDE_IOW[0:1]]# (STOP[0:1]#), IDE_IORDY[0:1]# (DDMARDY[0:1]) and IDE_IOR[0:1]# (HSTROBE[0:1]#) signal lines are not in effect until IDE_DREQ[0:1] and IDE_DACK[0:1]# are asserted. Figure 9-32. Initiating an UltraDMA Data Out Burst Timing Diagram AMD Geode™ SC2200 Processor Data Book ZIORDY 32580B...

  • Page 398: Figure 9-33. Sustained Ultradma Data Out Burst Timing Diagram

    Figure 9-33. Sustained UltraDMA Data Out Burst Timing Diagram 2CYC 2CYC Electrical Specifications AMD Geode™ SC2200 Processor Data Book...

  • Page 399: Figure 9-34. Device Pausing An Ultradma Data Out Burst Timing Diagram

    IDE_IORDY[0:1]# (DDMARDY[0:1]#) is de-asserted. If the t timing is not satisfied, the device may receive up to two additional datawords from the host. Figure 9-34. Device Pausing an UltraDMA Data Out Burst Timing Diagram AMD Geode™ SC2200 Processor Data Book 32580B after...

  • Page 400: Figure 9-35. Host Terminating An Ultradma Data Out Burst Timing Diagram

    Note: The definitions for the IDE_IOW[0:1]# (STOP[0:1]#), IDE_IORDY[0,1]# (DDMARDY[0:1]#) and IDE_IOR[0:1]# (HSTROBE[0:1]#) signal lines are no longer in effect after IDE_DREQ[0:1] and IDE_DACK[0:1]# are de-asserted. Figure 9-35. Host Terminating an UltraDMA Data Out Burst Timing Diagram Electrical Specifications IORDYZ AMD Geode™ SC2200 Processor Data Book...

  • Page 401: Figure 9-36. Device Terminating An Ultradma Data Out Burst Timing Diagram

    Note: The definitions for the IDE_IOW[0:1]# (STOP[0:1]#), IDE_IORDY[0:1]# (DDMARDY[0:1]#) and IDE_IOR[0:1]# (HSTROBE[0:1]#) signal lines are no longer in effect after IDE_DREQ[0:1] and IDE_DACK[0:1]# are de-asserted. Figure 9-36. Device Terminating an UltraDMA Data Out Burst Timing Diagram AMD Geode™ SC2200 Processor Data Book IORDZ 32580B...

  • Page 402: Universal Serial Bus (Usb) Interface

    (Monotonic) from 90% to 10% of the D_Port lines Average bit rate 1.5 Mbps ± 1.5% μs at 1.5 Mbps Host (downstream), Note 4 9-38 Host (downstream), Note 4 9-38 Function (downstream), Note 4 AMD Geode™ SC2200 Processor Data Book...
  • Page 403 Note 4. Measured at the crossover point of differential data signals (DPOS_PORT1,2,3 and DNEG_PORT1,2,3). Note 5. EOP is the End of Packet where DPOS_PORT (Min). Note 6. C = 350 pF. AMD Geode™ SC2200 Processor Data Book 32580B Unit Figure Comments –150 9-38 μs...

  • Page 404: Figure 9-37. Data Signal Rise And Fall Timing Diagram

    Data Lines = 350 pF USB_DJ11 USB_DJD21 USB_DJU21 Crossover Points (1.3-2.0) V USB_DJ11 USB_DJD21 USB_DJU21 Paired Transitions period_F USB_DJ12 period_L USB_DJD22 period_L USB_DJU22 Electrical Specifications Rise Time Fall Time USB_R1,2 USB_F1,2 USB_DJ12 USB_DJD22 USB_DJU22 AMD Geode™ SC2200 Processor Data Book...

  • Page 405: Figure 9-39. Eop Width Timing Diagram

    Figure 9-39. EOP Width Timing Diagram period_F period_L Differential Data Lines Consecutive Transitions period_F period_L period_L Figure 9-40. Receiver Jitter Tolerance Timing Diagram AMD Geode™ SC2200 Processor Data Book Data Crossover Level Source: USB_SE1, USB_DE1 Receiver: USB_DE2 USB_RE11, USB_RE21,...

  • Page 406: Serial Port (Uart)

    (Note 1) 1.48 1.78 ± 0.87% ± 2.0% ± 2.5% ± 6.5% Electrical Specifications Unit Comments Transmitter Receiver Transmitter Receiver Transmitter Receiver + 15 Transmitter, Variable µs Transmitter, Fixed µs Receiver Transmitter Receiver Transmitter Receiver AMD Geode™ SC2200 Processor Data Book...

  • Page 407: Figure 9-42. Fast Ir (Mir And Fir) Timing Diagram

    MIR mode. It is determined by the M_PWID field (bits [4:0]) in the MIR_PW register at offset 01h in bank 6 of logical device 5. Figure 9-42. Fast IR (MIR and FIR) Timing Diagram AMD Geode™ SC2200 Processor Data Book (Note 1) ± 0.1% ±...

  • Page 408: Figure 9-43. Standard Parallel Port Typical Data Exchange Timing Diagram

    Note 1. Times are system dependent and are therefore not tested. BUSY ACK# PD[7:0] STB# Figure 9-43. Standard Parallel Port Typical Data Exchange Timing Diagram AMD Geode™ SC2200 Processor Data Book Electrical Specifications Unit Comments Note 1 Note 1 Note 1...

  • Page 409: Figure 9-44. Enhanced Parallel Port Timing Diagram

    EPDW PD[7:0] hold after DSTRB# or EPDH ASTRB# inactive WW19a WRITE# DSTRB# ASTRB# WST19a PD[7:0] WPDS WAIT# Figure 9-44. Enhanced Parallel Port Timing Diagram AMD Geode™ SC2200 Processor Data Book WPDH WEST WW19ia 32580B Unit Comments WST19a EPDH Valid EPDW...

  • Page 410: Figure 9-45. Ecp Forward Mode Timing Diagram

    ECHHF BUSY inactive after STB# active ECHLF STB# active after BUSY inactive ECLLF PD[7:0] AFD# STB# BUSY Figure 9-45. ECP Forward Mode Timing Diagram ECDHF ECDSF ECHLF ECLHF ECHHF AMD Geode™ SC2200 Processor Data Book Electrical Specifications Unit Comments ECLLF...

  • Page 411: Figure 9-46. Ecp Reverse Mode Timing Diagram

    ACK# inactive after AFD# inactive ECHHR AFD# active after ACK# inactive ECHLR ACK# active after AFD# active ECLLR PD[7:0] BUSY# ACK# AFD# Figure 9-46. ECP Reverse Mode Timing Diagram AMD Geode™ SC2200 Processor Data Book ECDSR ECHLR ECLHR ECHHR 32580B Unit Comments ECDHR ECLLR...

  • Page 412: Figure 9-47. Ac97 Reset Timing Diagram

    SYNC active high pulse width SYNC_HIGH SYNC inactive to BIT_CLK startup SYNC_IA delay SYNC BIT_CLK Figure 9-48. AC97 Sync Timing Diagram 162.8 RST2CLK RST_LOW 162.8 SYNC_IA SYNC_HIGH AMD Geode™ SC2200 Processor Data Book Electrical Specifications Unit Comments µs Unit Comments µs...

  • Page 413: Figure 9-49. Ac97 Clocks Diagram

    AC97_CLK fall/rise time AC97_CLK_FR AC97_CLK output edge-to- AC97_CLK_J edge jitter Note 1. Worst case duty cycle restricted to 40/60. BIT_CLK SYNC AC97_CLK AMD Geode™ SC2200 Processor Data Book Table 9-38. AC97 Clocks Parameters 12.288 81.4 32.56 40.7 48.84 32.56 40.7 48.84...

  • Page 414: Figure 9-50. Ac97 Data Timing Diagram

    Sync out hold after falling edge of AC97_SH BIT_CLK BIT_CLK SDATA_OUT/SYNC SDATA_IN, SDATA_IN2 Table 9-39. AC97 I/O Timing Parameters 15.0 10.0 AC97_SV AC97_OV AC97_S AC97_H Figure 9-50. AC97 Data TIming Diagram Electrical Specifications Unit Comments AC97_SH AC97_OH AMD Geode™ SC2200 Processor Data Book...

  • Page 415: Figure 9-51. Ac97 Rise And Fall Timing Diagram

    SDATA_IN fall time trise SDATA_OUT rise time DOUT tfall SDATA_OUT fall time DOUT BIT_CLK SYNC SDATA_IN SDATA_OUT Figure 9-51. AC97 Rise and Fall Timing Diagram AMD Geode™ SC2200 Processor Data Book Unit trise tfall trise tfall SYNC SYNC trise tfall trise tfall...

  • Page 416: Figure 9-52. Ac97 Low Power Mode Timing Diagram

    End of Slot 2 to BIT_CLK, s2_pdown SDATA_IN low SYNC BIT_CLK SDATA_OUT SDATA_IN Note: BIT_CLK is not to scale Figure 9-52. AC97 Low Power Mode Timing Diagram Unit µs Slot 1 Slot 2 s2_pdown AMD Geode™ SC2200 Processor Data Book Electrical Specifications Comments...

  • Page 417: Figure 9-53. Pwrbtn# Trigger And Onctl# Timing Diagram

    Table 9-43. Power Management Event (GPWIO) and ONCTL# Timing Parameters Symbol Parameter Power management event to ONCTL# assertion GPWIOx ONCTL# PWRCNT1 PWRCNT2 Figure 9-54. GPWIO and ONCTL# Timing Diagram AMD Geode™ SC2200 Processor Data Book Unit PBTNP PBTNE PBTNE Unit 32580B Comments Note 1 PBTNP...

  • Page 418: Figure 9-55. Power-Up Sequencing With Pwrbtn# Timing Diagram

    V If PWRBTN# max is exceeded, ONCTL# will go inactive. System determines when V and V are applied, hence there is no maximum constraint. POR# must not glitch during active time. AMD Geode™ SC2200 Processor Data Book CORE...

  • Page 419: Figure 9-56. Power-Up Sequencing Without Pwrbtn# Timing Diagram

    Asserting POR# has no effect on ACPI. If POR# is asserted and ACPI was active prior to POR#, then ACPI will remain active after POR#. Therefore, BIOS must ensure that ACPI is inactive before GPIO63 is pulsed low. AMD Geode™ SC2200 Processor Data Book -100...

  • Page 420: Jtag Interface

    Non-test inputs setup time TDI, TMS hold time Non-test inputs hold time IH(Min) 1.5V IL(Max) Figure 9-57. TCK Measurement Points and Timing Diagram Table 9-46. JTAG Timing Parameters Electrical Specifications Unit Comments 50 pF load AMD Geode™ SC2200 Processor Data Book...

  • Page 421: Figure 9-58. Jtag Test Timing Diagram

    Electrical Specifications TDI, Output Signals Input Signals AMD Geode™ SC2200 Processor Data Book Figure 9-58. JTAG Test Timing Diagram 32580B...
  • Page 422 32580B Electrical Specifications AMD Geode™ SC2200 Processor Data Book...

  • Page 423: 10.0Package Specifications

    (Nominal) Frequency Power (W) 1.8V 266 MHz AMD Geode™ SC2200 Processor Data Book 10.0Package Specifications ) of the pack- A maximum junction temperature is not specified since a maximum case temperature is. Therefore, the following equation can be used to calculate the maximum thermal...

  • Page 424: Figure 10-1. Heatsink Example

    SC2200 processor, which is always less than 4 Watts. CA = 45/9 = 5 Package Specifications (max) = 40°C. − T 85 − 40 =8). (max) = 40°C. − T 85 − 40 AMD Geode™ SC2200 Processor Data Book...

  • Page 425: Physical Dimensions

    Package Specifications 32580B 10.2 Physical Dimensions The figures in this section provide the mechanical package outlines for the BGU481 (Thermally Enhanced Ball Grid Array) package. Figure 10-2. BGU481 Package - Top View AMD Geode™ SC2200 Processor Data Book...

  • Page 426: Amd Geode™ Sc2200 Processor Data Book

    32580B Package Specifications Figure 10-3. BGU481 Package - Bottom View AMD Geode™ SC2200 Processor Data Book...

  • Page 427: Appendix A Support Documentation

    The “B” suffix denotes a maximum I Table 9-7 on page 373 for details. Consult your local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations possibly not listed. AMD Geode™ SC2200 Processor Data Book...

  • Page 428: Data Book Revision History

    32580B Data Book Revision History This document is a report of the revision/creation process of the data book for the AMD Geode™ SC2200 processor. Any revisions (i.e., additions, deletions, parameter corrections, etc.) are recorded in the table below. Revision #...
  • Page 429 One AMD Place • P.O. Box 3453 • Sunnyvale, CA 94088-3453 USA • Tel: 408-749-4000 or 800-538-8450 • TWX: 910-339-9280 • TELEX: 34-6306...

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