AMD SB600 Technical Reference Manual page 134

Field Name
Dma2_Ch7Cnt
Dma2_Ch7Cnt register
Field Name
Dma_Status
Dma_Status register
Field Name
Dma_WriteRequest
Dma_WriteRequest register
Field Name
Dma_WriteMask
Dma_WriteMask register
Field Name
Dma_WriteMode
Dma_WriteMode register
Field Name
Dma_Clear
Dma_Clear register
Field Name
Dma_Clear
Dma_Clear register
Field Name
Dma_ClrMask
Dma_ClrMask register
Field Name
Dma_AllMask
Dma_AllMask register
Field Name
Reserved
WarmBoot
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Dma_Ch7Cnt - RW – 8 bits - [IO_Reg: CEh]
Bits Default
7:0 00h Channel 7 DMA base and current count
Dma_Status - RW – 8 bits - [IO_Reg: D0h]
Bits Default
7:0 00h DMA2 status register
Dma_WriteRequest - RW – 8 bits - [IO_Reg: D2h]
Bits Default
7:0 00h DMA2 request register
Dma_WriteMask - RW – 8 bits - [IO_Reg: D4h]
Bits Default
7:0 00h DMA2 channel mask register
Dma_WriteMode - RW – 8 bits - [IO_Reg: D6h]
Bits Default
7:0 00h DMA2 mode register
Dma_Clear - RW – 8 bits - [IO_Reg: D8h]
Bits Default
7:0 00h Channel 4-7 clear byte pointer
Dma_Clear - RW – 8 bits - [IO_Reg: DAh]
Bits Default
7:0 00h Channel 4-7 DMA master clear
Dma_ClrMask - RW – 8 bits - [IO_Reg: DCh]
Bits Default
7:0 00h Channel 4-7 DMA Clear Mask
Dma_ClrMask - RW – 8 bits - [IO_Reg: DEh]
Bits Default
7:0 00h DMA2 mask register
NCP_Error - RW – 8 bits - [IO_Reg: F0h]
Bits Default
6:0 00h
7 0b Warm or cold boot indicator
0 – Cold
1 – Warm, this bit is set when any value is written to this
register;
Description
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Description
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Description
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary Page 134