AMD SB600 Technical Reference Manual page 101

Field Name
Base Address 2 register
Field Name
Base Address 3
Base Address 3 register
Field Name
Base Address 4
Base Address 4 register
Field Name
Base Address 5
Base Address 5 register
Field Name
Cardbus CIS Pointer
Cardbus CIS Pointer register
Field Name
Subsystem Vendor ID
Subsystem Vendor ID register
Field Name
Subsystem ID
Subsystem ID register
Expansion ROM Base Address - R - 8 bits - [PCI_Reg: 30h]
Field Name
Expansion ROM Base
Address
Expansion ROM Base Address register
Field Name
Capability Pointer
Capability Pointer register
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Base Address 2- R - 32 bits - [PCI_Reg: 18h]
Bits Default
Base Address 3- R - 32 bits - [PCI_Reg: 1Ch]
Bits Default
31:0 0000_000 Not used and is hardcoded to 0.
0h
Base Address 4- R - 32 bits - [PCI_Reg: 20h]
Bits Default
31:0 0000_000 Not used and is hardcoded to 0.
0h
Base Address 5- R - 32 bits - [PCI_Reg: 24h]
Bits Default
31:0 0000_000 Not used and is hardcoded to 0.
0h
Cardbus CIS Pointer- R - 32 bits - [PCI_Reg: 28h]
Bits Default
31:0 0000_000 Not used and is hardcoded to 0.
0h
Subsystem Vendor ID- W - 16 bits - [PCI_Reg: 2Ch]
Bits Default
15:0 0000h Write once.
Subsystem ID- W - 16 bits - [PCI_Reg: 2Eh]
Bits Default
15:0 0000h Write once.
Bits Default
7:0 00h Not used and is hardcoded to 0.
Capability Pointer - R - 8 bits - [PCI_Reg: 34h]
Bits Default
7:0 B0/00h For K8 system default value is B0h; for P4 system default
value is 00h.
Description
Description
Description
Description
Description
Description
Description
Description
Description
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary Page 101