AMD SB600 Technical Reference Manual page 172

Field Name
AutoArbDisWaitTime
HPET_DisablePeriodic
HPET_Load
ASFRemoteDelay
RstCstate/9E
AutoArbDisWaitTime register
Field Name
ProgramIo4Mask
ProgramIo4RangeLo
ProgramIo4RangeLo register
Field Name
ProgramIo4RangeHi
ProgramIo4RangeHi register
Field Name
ProgramIo5Mask
ProgramIo5RangeLo
ProgramIo5RangeLo register
Field Name
ProgramIo5RangeHi
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
AutoArbDisWaitTime - RW - 8 bits - [PM_Reg: 9Fh]
Bits Default
3:0 0h This defines the amount of time (in 2us increment) that SB will
hold ARB_DIS set after breaking from C3. This is to allow
sometime for CPU to resume from C3 before allowing any bus
mastering to the memory. This timer has an uncertainty of -
2us. This applies to K8 C1e or P4 LVL3 if AutoArbDisEn is set.
4 0h Set to 1 to make Periodical capability bit appear to be 0.
5 0h Set to 1 to make HPET timer load the new value in periodical
mode
6 0h Set to 1 to delay the remote action(reset,power dwon..)
7 0h Set to 1 to make state machine of C state reset by pcirst,
otherwise rsmrst
Programlo4RangeLo - RW – 8 bits - [PM_Reg: A0h]
Bits Default
3:0 0h These four bits are used to mask the least 4 bits of the 16 bit
I/O. If bit [3] is set, then bit [3] of the I/O address is not
compared. If it is not set, then bit [3] of the monitored
address is 0. The same applies for the other three bits [2:0].
For example, if x15=80h, x14[7:4]=Ah, and x14[3:0]=3h, then
the monitored range is 80A4h : 80A0h (bit 0 and 1 are
masked)
7:4 0h I/O range base address; these bits define the least significant
byte of the 16 bit I/O range base address that is programmed
to trigger SMI# when the address is accessed. Bit 7
corresponds to Addr[7] and bit 4 to Addr[4].
ProgramIo4RangeHi - RW – 8 bits - [PM_Reg: A1h]
Bits Default
7:0 00h I/O range base address; these bits define the most significant
byte of the 16 bit I/O range base address. Bit 7 corresponds
to Addr[15] and bit 0 to Addr[8].
Programlo5RangeLo - RW – 8 bits - [PM_Reg: A2h]
Bits Default
3:0 0h These four bits are used to mask the least 4 bits of the 16 bit
I/O. If bit [3] is set, then bit [3] of the I/O address is not
compared. If it is not set, then bit [3] of the monitored
address is 0. The same applies for the other three bits [2:0].
For example, if x15=80h, x14[7:4]=Ah, and x14[3:0]=3h, then
the monitored range is 80A4h : 80A0h (bit 0 and 1 are
masked)
7:4 0h I/O range base address; these bits define the least significant
byte of the 16 bit I/O range base address that is programmed
to trigger SMI# when the address is accessed. Bit 7
corresponds to Addr[7] and bit 4 to Addr[4].
ProgramIo5RangeHi - RW – 8 bits - [PM_Reg: A3h]
Bits Default
7:0 00h I/O range base address; these bits define the most significant
byte of the 16 bit I/O range base address. Bit 7 corresponds
to Addr[15] and bit 0 to Addr[8].
Description
Description
Description
Description
Description
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary Page 172