AMD SB600 Technical Reference Manual page 191

Field Name
Interrupt Pin
Interrupt Pin Register: This register identifies the interrupt pin a device uses. Since the IDE host controller uses
IRQ14, this value is supposed to be 00. However, the IDE controller will generate the PCI interrupt INTA# signal on
the PCI bus. Therefore, this pin register is set to 01h.
Field Name
Minimum Grant
Min_gnt Register: This register specifies the desired settings for how long of a burst the IDE host controller needs
assuming a clock rate of 33MHz. The value specifies a period of time in units of ¼ microseconds.
Field Name
Maximum Latency
Max_latency Register: This register specifies the Maximum Latency time required before the IDE host controller as
a bus-master can start an accesses.
Field Name
Primary Slave Data
Register Command
Recovery Width
Primary Slave Data
Register Command width
Primary Master Data
Register Command
Recovery Width
Primary Master Data
Register Command
Width
Reserved
IDE PIO Timing Register: This register controls the IDE interface and selects the timing of the IDE PIO bus-master
cycles.
Note: Relation of setting value and actual timing of each mode are
PIO Mode 4
Command Width 2(90ns)
Recover Width 0(30ns)
The above timings are valid and A-Link clock is always 66MHz.
Actual timing is setting value + 1 A-Link clock cycle.
IDE Legacy DMA (Multi-words DMA) Timing Modes - RW - 32 bits - [PCI_Reg:44h]
Field Name
Primary Slave DMA
Command Recovery
Width
Primary Slave DMA
Command Width
Primary Master DMA
Command Recovery
Width
Primary Master DMA
Command Width
Reserved
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Interrupt Pin - R - 8 bits - [PCI_Reg:3Dh]
Bits Default
7:0 01h Hard-wired to 01h.
Min_gnt - R - 8 bits - [PCI_Reg:3Eh]
Bits Default
7:0 00h Hard-wired to 0's and always read as 0's.
Max_latency - R - 8 bits - [PCI_Reg:3Fh]
Bits Default
7:0 00h Hard-wired to 0's and always read as 0's.
IDE PIO Timing - RW - 32 bits - [PCI_Reg:40h]
Bits Default
3:0 9h Slave Data register command recovery width for Primary IDE
bus slave PIO device.
7:4 9h Slave Data register command width for Primary IDE bus slave
PIO device.
11:8 9h Master Data register command recovery width for primary IDE
bus Master PIO device.
15:12 9h Master Data register command width for Primary IDE bus
Master PIO device.
31:16 0000h Reserved. Always read as 0's
3 2
2(90ns) 3(120ns)
2(90ns) 4(150ns)
Bits Default
3:0 Fh Slave DMA command recovery width for Primary IDE bus
Slave DMA device.
7:4 Fh Slave DMA command width for Primary IDE bus Slave DMA
device.
11:8 Fh Master DMA Command recovery width for primary IDE bus
Master DMA device.
15:12 Fh Master DMA Command width for Primary IDE bus Master
DMA device.
31:16 0h Reserved. Always read as 0's
Description
Description
Description
Description
1 0
4(150ns) 9(270ns)
7(240ns) 9(270ns)
Description
IDE Controller (Device 20, Function 1)
Proprietary Page 191