AMD SB600 Technical Reference Manual page 248

Stream Descriptor BDL Pointer Lower Base Address – RW – 32 bits
Field Name
Reserved
Buffer Descriptor List
Lower Base Address
Stream Descriptor BDL Pointer Upper Base Address – RW – 32 bits
Field Name
Buffer Descriptor List
Upper Base Address
Wall Clock Counter Alias – R – 32 bits – [Mem_Reg: Base + 2030h]
Field Name
Wall Clock Counter Alias
Stream Descriptor Link Position in Buffer Alias – R – 32 bits
Field Name
Link Position in Buffer
Alias
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Input Stream 0 - [Mem_Reg: Base + 98h]
Input Stream 1 - [Mem_Reg: Base + B8h]
Input Stream 2 - [Mem_Reg: Base + D8h]
Input Stream 3 - [Mem_Reg: Base + F8h]
Output Stream 0 - [Mem_Reg: Base + 138h]
Output Stream 2 - [Mem_Reg: Base + 158h]
Output Stream 3 - [Mem_Reg: Base + 178h]
Bits Default
6:0 00h Hardwired to 0's to force 128 byte alignment of the BDL.
31:7 0000000h Upper 25 bits of the lower 32 bit address of the Buffer
Descriptor List. This value should not be modified except
when the Run bit is "0".
Input Stream 0 - [Mem_Reg: Base + 9Ch]
Input Stream 1 - [Mem_Reg: Base + BCh]
Input Stream 2 - [Mem_Reg: Base + DCh]
Input Stream 3 - [Mem_Reg: Base + FCh]
Output Stream 0 - [Mem_Reg: Base + 11Ch]
Output Stream 1 - [Mem_Reg: Base + 13Ch]
Output Stream 2 - [Mem_Reg: Base + 15Ch]
Output Stream 3 - [Mem_Reg: Base + 17Ch]
Bits Default
31:0 00000000 Upper 32 bit address of the Buffer Descriptor List. This
h value should not be modified except when the Run bit is
"0".
Bits Default
31:0 00000000 An alias of the Wall Clock Counter register at offset 30h. It
h behaves exactly the same as if the Wall Clock Counter
register were being read directly.
Input Stream 0 - [Mem_Reg: Base + 2084h]
Input Stream 1 - [Mem_Reg: Base + 20A4h]
Input Stream 2 - [Mem_Reg: Base + 20C4h]
Input Stream 3 - [Mem_Reg: Base + 20E4h]
Output Stream 0 - [Mem_Reg: Base + 2104h]
Output Stream 1 - [Mem_Reg: Base + 2124h]
Output Stream 2 - [Mem_Reg: Base + 2144h]
Output Stream 3 - [Mem_Reg: Base + 2164h]
Bits Default
31:0 00000000 An alias of the Link Position in Buffer register of each
h Stream Descriptor.
Description
Description
Description
Description
HD Audio Controllers Registers
Proprietary Page 248