AMD SB600 Technical Reference Manual page 273

Field Name
PCICLK4Enable
PCICLK5Enable
PCICLK6Enable
PCICLK7Enable
Reserved
PCICLK Enable bits
Field Name
GNT Bus Idle check
enable
Memory Read Burst
Size
IOMode
MemReadCmdMatch
SubDecodeEnable
Misc control Register
Field Name
Autoclkrun Enable
Autoclkrun count
Auto ClockRun control register
Dual Address Cycle Enable and PCIB_CLK_Stop Override - RW - 16 bits - [PCI_Reg: 50h]
Field Name
PCIB_Dual_EN_up
PCIB_Dual_EN_dn
Reserved
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
PCICLK Enable Bits- RW - 8 bits - [PCI_Reg: 4Ah]
Bits Default
0 1b
1 1b
2 1b
3 1b
7:4 3h
Misc Control RW - 8 bits - [PCI_Reg: 4Bh]
Bits Default
0 0b
4:1 0h
5 0b
6 0b
7 0b
AutoClockRun control RW - 32 bits - [PCI_Reg: 4Ch]
Bits Default
0 0b
31:1 0000_000
0h
Bits Default
0 0b
1 0b
5:2 0h
Description
33MHz PCICLK4 enable.
33MHz PCICLK 5 enable.
33MHz PCICLK 6 enable.
33MHz PCICLK 7 enable.
Reserved
Description
When enabled, the PCI arbiter checks for the Bus Idle
before asserting GNT#.
Specifies up to how many double words burst to support
during an upstream or downstream memory read.
[4:1] =
1xxx: Burst up to 16 double words
01xx: Burst up to 8 double words
001x: Burst up to 4 double words
0001: Burst up to 2 double words
Others: Burst up to 8 double words
Note 1: It has no effect on a downstream normal memory
read (other than read line and read multiple), which has no
burst in this design.
Note 2: It has no effective on an upstream memory read if
the read is prefetchable as specified by reg0x64[7],
reg0x64[21], and reg0x40[4], because a prefetchable read
can have unlimited burst.
Control bit to change the IO addressing mode to 32/16 bit.
0 – 16 bits;
1 – 32 bit.
Control bit to enable the match of memory read/memory
read line commands when there is a read command in the
delay queue.
Control bit for the subtractive decode status (09h).
0 – No subtractive decode;
1 – Whether the subtractive decode is enabled depends on
reg0x40[5].
Description
Enables the auto clkrun functionality
Number of cycles after which the secondary clock stops
when clkrun is enabled
Description
Enables decoding of Dual Address Cycle on secondary side
for upstream memory transactions
Enables decoding of Dual Address Cycle on secondary side
for downstream memory transactions
Host PCI Bridge Registers (Device 20, Function 4)
Proprietary Page 273