AMD SB600 Technical Reference Manual page 200

Field Name
Revision ID
Class Code
Revision ID/Class Code Register: This read only register contains the device's revision information and generic
function.
Field Name
Cache Line Size
Cache Line Size Register: This register specifies the system cache line size.
Field Name
Latency Timer
Latency Timer Register: This register specifies the value of the Latency Timer in units of PCICLKs.
Field Name
Header Type
Header Type Register: This register identifies the type of the predefined header in the configuration space. Since
SB600 is a multifunction device, the most significant bit is set.
Field Name
BIST
Built-in Self Test Register: This register is used for control and status for Built-in Self Test. Ac97 has no BIST
modes.
Field Name
MemoryIndicator
Type
Prefetchable
Reserved
BAR0
Field Name
MemoryIndicator
Type
Prefetchable
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Revision ID/Class Code - R - 32 bits - [PCI_Reg: 08h]
Bits Default
7:0 00h Revision ID.
31:8 040100h Class Code.
Cache Line Size - RW - 8 bits - [PCI_Reg: 0Ch]
Bits Default
7:0 00h Cache Line Size.
Latency Timer - RW - 8 bits - [PCI_Reg: 0Dh]
Bits Default
7:0 00h Latency Timer.
Header Type - R - 8 bits - [PCI_Reg: 0Eh]
Bits Default
7:0 80h Header Type.
BIST- R – 8 bits – [PCI_Reg: 0Fh]
Bits Default
7:0 00h BIST register.
Base Address Reg 0- RW - 32 bits – [PCI_Reg: 10h]
Bits Default
0 0b
2:1 00b
3 0b
7:4 0h
31:8 0000_00h
Base Address Reg 1- RW - 32 bits – [PCI_Reg: 14h]
Bits Default
0 0b
2:1 00b
3 0b
Description
Description
Description
Description
Description
Description
Always 0; meaning it is always memory mapped
Always 0; meaning it can be located anywhere in 32 bit
address space
Always 0; meaning it is not prefetchable
Always 0; meaning the memory mapped registers occupy
256 bytes
Base address register 0. Defines the base address for the
memory mapped register space of audio. If index 50h, bit 3
is set, bits [13:8] of this register become unwritable. The
effect will cause the OS to allocate a wider memory map for
this controller.
Description
This bit will return 1 if index 50h, bit [1] is set. 1 means IO
mapping
Always 0; meaning that it can be located anywhere in 32 bit
address space.
Always 0; meaning that it is not prefetchable.
AC '97 Controller Functional Descriptions
Proprietary Page 200