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2.3.3.1.3
System Reset Register (IO CF9)
Note: Refer to PM IO reg x85 for a detailed description. This register has been designed to be dual-port
accessible.
2.3.3.2
Power Management (PM) Registers
The power management (PM) block is resident in the PCI/LPC/ISA bridge. The PM registers are accessed
via IO mapped registers xCD6h and xCD7h. The index address is first programmed into IO register xCD6h.
Read or write values are accessed through IO register xCD7h.
SmiWakeUpEventEnable1
SmiWakeUpEventEnable2
SmiWakeUpEventEnable3
SmiWakeUpEventStatus1
SmiWakeUpEventStatus2
SmiWakeUpEventStatus3
InactiveTmrEventEnable1
InactiveTmrEventEnable2
InactiveTmrEventEnable3
InactiveTmrEventEnable4
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Register Name
MiscControl
MiscStatus
PmTmr1InitValue
PmTmr1CurValue
PwrLedExtEvent
PwrLedExtEvent
AcpiStatus
AcpiEn
S1AgpStpEn
PmTmr2InitValue
PmTmr2CurValue
Programlo0RangeLo
Programlo0RangeHi
ProgramIo1RangeLo
ProgramIo1RangeHi
ProgramIo2RangeLo
ProgramIo2RangeHi
ProgramIo3RangeLo
ProgramIo3RangeHi
ProgramIoEnable
IOMonitorStatus
AcpiPm1EvtBlkLo
AcpiPm1EvtBlkHi
AcpiPm1CntBlkLo
AcpiPm1CntBlkHi
AcpiPmTmrBlkLo
AcpiPmTmrBlkHi
CpuControlLo
CpuControlHi
AcpiGpe0BlkLo
AcpiGpe0BlkHi
AcpiSmiCmdLo
AcpiSmiCmdHi
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary
Offset Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
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