AMD SB600 Technical Reference Manual page 252

Field Name
Latency Timer
Latency Timer Register: This register specifies the value of the Latency Timer in units of PCICLKs.
Field Name
Header Type
Header Type Register: This register identifies the type of the predefined header in the configuration space. Since
THE SB600 is a multifunction device, the most significant bit is set.
Field Name
BIST
Built-in Self Test Register: This register is used for control and status for Built-in Self Test. LPC has no BIST modes.
Field Name
Base Address 0
This register is write-only. Reading it always returns 0000_0000h. It has an internal value used as base address for
APIC memory space. Writing to the register will change its internal value, but only bit[31:5] is overwritten, and
bit[4:0] is hardwired to 00000b. The default internal value is FEC0_0000h.
Subsystem ID & Subsystem Vendor ID – RW - 32 bits - [PCI_Reg: 2Ch]
Field Name
Subsystem Vendor ID
Subsystem ID
This 4-byte register is a write-once & read-only afterward register. The BIOS writes this register once (all 4 bytes at
once) and software reads its value (when needed).
Field Name
Capabilities Pointer
Reserved
Field Name
Reserved
DMA Enable
Reserved
IO Port Decode Enable Register 1- RW - 8 bits - [PCI_Reg: 44h]
Field Name
Parallel Port Enable 0
Parallel Port Enable 1
Parallel Port Enable 2
Parallel Port Enable 3
Parallel Port Enable 4
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Latency Timer - R - 8 bits - [PCI_Reg: 0Dh]
Bits Default
7:0 00h Latency Timer.
Header Type - R - 8 bits - [PCI_Reg: 0Eh]
Bits Default
7:0 80h Header Type.
BIST- R - 8 bits - [PCI_Reg: 0Fh]
Bits Default
7:0 00h BIST.
Base Address Reg 0- RW* - 32 bits - [PCI_Reg: 10h]
Bits Default
31:0 FEC0_0000h
Bits Default
15:0 0000h
31:16 0000h
Capabilities Pointer - R - 32 bits - [PCI_Reg: 34h]
Bits Default
7:0 00h
31:8 000000h
PCI Control - RW - 8 bits - [PCI_Reg: 40h]
Bits Default
1:0 0h
2 0b Setting it to 1 enables lpc DMA cycle. Note: 32-bit DMA is not
supported. Transfer size: Channels 0-3: 8 bits, channels 5-7: 16
bits.
7:3 00h
Bits Default
0 0b Port enable for parallel port, 378-37fh
1 0b Port enable for parallel port, 778-77fh
2 0b Port enable for parallel port, 278-27fh
3 0b Port enable for parallel port, 678-67fh
4 0b Port enable for parallel port, 3bc-3bfh
Description
Description
Description
Description
Base address register 0.
Description
Subsystem Vendor ID.
Subsystem ID.
Description
When reg0x78[1] (msi on) is 0, this field reads 0; when
reg0x78[1] is 1, this field reads 80h, pointing to the starting
address of MSI capability register
Description
Description
LPC ISA Bridge (Device 20, Function 3)
Proprietary Page 252