AMD SB600 Technical Reference Manual page 26

Field Name
Number of Ports(NP)
Supports External SATA
(SXS)
Enclosure Management
Supported (EMS)
Command Completion
Coalescing Supported
(CCCS)
Number of Command
Slots (NCS)
Partial State Capable
(PSC)
Slumber State Capable
(SSC)
PIO Multiple DRQ Block
(PMD)
FIS-based Switching
Supported (FBSS)
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
HBA Capabilities – R - 32bits [Mem_reg: ABAR + 00h]
Bits Default
4:0 00011b
5 0b
6 0b
7 1b
12:8 11111b
13 1b
14 1b
15 1b
16 0b
Description
0's based value indicating the maximum number of ports
supported by the HBA silicon. A maximum of 32 ports can be
supported. A value of '0h', indicating one port, is the
minimum requirement. Note that the number of ports
indicated in this field may be more than the number of ports
indicated in the GHC.PI register.
When set to '1', indicates that the HBA has one or more
Serial ATA ports that has a signal only connector that is
externally accessible. If this bit is set to '1', software may
refer to the PxCMD.ESP bit to determine whether a specific
port has its signal connector externally accessible as a signal
only connector (i.e. power is not part of that connector).
When the bit is cleared to '0', indicates that the HBA has no
Serial ATA ports that have a signal only connector externally
accessible.
When set to '1', indicates that the HBA supports enclosure
management. When enclosure management is supported,
the HBA has implemented the EM_LOC and EM_CTL global
HBA registers. When cleared to '0', indicates that the HBA
does not support enclosure management and the EM_LOC
and EM_CTL global HBA registers are not implemented.
When set to '1', indicates that the HBA supports command
completion coalescing. When command completion
coalescing is supported, the HBA has implemented the
CCC_CTL and the CCC_PORTS global HBA registers.
When cleared to '0', indicates that the HBA does not support
command completion coalescing and the CCC_CTL and
CCC_PORTS global HBA registers are not implemented.
0's based value indicating the number of command slots per
port supported by this HBA. A minimum of 1 and maximum
of 32 slots per port can be supported. The same number of
command slots is available on each implemented port.
Indicates whether the HBA can support transitions to the
Partial state. When cleared to '0', software must not allow
the HBA to initiate transitions to the Partial state via
aggressive link power management nor the PxCMD.ICC field
in each port, and the PxSCTL.IPM field in each port must be
programmed to disallow device initiated Partial requests.
When set to '1', HBA and device initiated Partial requests can
be supported.
Indicates whether the HBA can support transitions to the
Slumber state. When cleared to '0', software must not allow
the HBA to initiate transitions to the Slumber state via
aggressive link power management nor the PxCMD.ICC field
in each port, and the PxSCTL.IPM field in each port must be
programmed to disallow device initiated Slumber requests.
When set to '1', HBA and device initiated Slumber requests
can be supported.
If set to '1', the HBA supports multiple DRQ block data
transfers for the PIO command protocol. If cleared to '0' the
HBA only supports single DRQ block data transfers for the
PIO command protocol.
When set to '1', indicates that the HBA supports Port
Multiplier FIS-based switching. When cleared to '0', indicates
that the HBA does not support FIS-based switching. AHCI
1.0 and 1.1 HBAs shall have this bit cleared to '0'.
SATA Registers (Device 18, Function 0)
Proprietary Page 26