AMD SB600 Technical Reference Manual page 272

Field Name
PCICLKStopEnable
PCICLKStopStatus
PCICLK0Enable
PCICLK1Enable
PCICLK2Enable
PCICLK3Enable
P2SControl
S2PControl
Clock control register
Field Name
Reserved
ArbiterEnable
Arbiter control register
Field Name
SMLT_Perf
Secondary MLT performance register
Field Name
PMLT_Perf
Primary MLT performance register
Field Name
PCDMA Device Enable
A
PCDMA Device Enable
B
Fast Back to Back Retry
Enable
Lock Operation Enable
Reserved
PCDMA device Enable bits
Field Name
Reserved
PCDMA Priority
Reserved
Priority Bits
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
CLKCTRL- RW - 8 bits - [PCI_Reg: 42h]
Bits Default
0 0b
1 0b
2 1b
3 1b
4 1b
5 1b
6 0b
7 0b
ARCTRL- RW - 8 bits - [PCI_Reg: 43h]
Bits Default
6:0 ffh
7 1b
SMLT_PERF- RW - 16 bits - [PCI_Reg: 44h]
Bits Default
15:0 0000h
PMLT_PERF- RW - 16 bits - [PCI_Reg: 46h]
Bits Default
15:0 0000h
PCDMA- RW - 8 bits - [PCI_Reg: 48h]
Bits Default
0 0b
1 0b
2 0b
3 1b
7:4 00h
Additional Priority- Bits RW - 8 bits - [PCI_Reg: 49h]
Bits Default
0 0b
1 0b
7:2 00h
Description
33MHz PCICLKs request bit; when '1,' 33 MHz PCI Clocks
are requested to stop.
Read only.
33MHz PCICLKs stop status: '1' stopped, '0' running.
33MHz PCICLK0 enable.
33MHz PCICLK1 enable.
33MHz PCICLK2 enable.
33MHz PCICLK3 enable.
P_CLK domain to S_CLK domain synch-up disable.
S_CLK domain to P_CLK domain synch-up disable.
Description
Reserved
Arbiter enable. '0' disabled to give PCIB the exclusive
ownership of the secondary bus.
Description
Count the total number of a burst being broken into multiple
transactions due to MLT timeout.
Description
Count the total number of a burst being broken into multiple
transactions due to MLT timeout.
Description
Device enable for request 3. Needs to be enabled when
there is a PCDMA device corresponding to request 3
Device enable for request 4. Heeds to be enabled when
there is a PCDMA device corresponding to request 4
Retry Fast Back to Back transactions on Write buffer full.
When reg0x40[2]=1, this bit should be set to 1 for the proper
operation of the PCI LOCK# function.
Reserved
Description
If enabled includes PCDMA request into high priority list
Reserved
Host PCI Bridge Registers (Device 20, Function 4)
Proprietary Page 272