AMD SB600 Technical Reference Manual page 178

Field Name
This register is located at the base address defined by CpuControl
Field Name
PLvl2
This register is located at the base address defined by CpuControl
Field Name
PLvl3
This register is located at the base address defined by CpuControl
Field Name
PLvl4
This register is located at the base address defined by CpuControl
Field Name
AcpiSsCnt
Reserved
This register is located at the base address defined by AcpiSsCntBlk
Field Name
GeventStatus
LEventStatus
TwarnStatus
Reserved
USBStatus
AC97Status
OtherThermStatus
GPM9Status
PCIeHotPlugStatus
ExtEvent0Status
ExtEvent1Status
PCIePmeStatus
GPM0Status
GPM1Status
GPM2Status
GPM3Status
GPM8Status
Gpio0Status
GPM4Status
GPM5Status
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
CLKVALUE - RW - 32 bits - [CpuControl:00h]
Bits Default
PLvl2 - R - 8 bits - [CpuControl:04h]
Bits Default
7:0 00h
PLvl3 – R – 8 bits - [CpuControl:05h]
Bits Default
7:0 00h
PLvl4 – R - 8 bits - [CpuControl:06h]
Bits Default
7:0 00h
AcpiSsCnt - RW - 8 bits - [AcpiSsCntBlk:00h]
Bits Default
0 0b
7:1 00h
EVENT_STATUS - RW - 32 bits - [AcpiGpe0Blk:00h]
Bits Default
7:0 00h
8 0b
9 0b
10
11 0b
12 0b
13 0b
14 0b
15 0b
16 0b
17 0b
18 0b
19 0b
20 0b
21 0b
22 0b
23 0b
24 0b
25 0b
26 0b
Description
Description
Reads to this register return all zeros; writes to this register
have no effect. Reads to this register generates a "enter C2
power" to the clock control logic (STPCLK logic).
Description
Reads to this register return all zeros; writes to this register
have no effect. Reads to this register generates a "enter C3
power" to the clock control logic (STPCLK logic).
Description
Reads to this register return all zeros; writes to this register
have no effect. Reads to this register generates a "enter C4
power" to the clock control logic (STPCLK logic).
Description
Reserved
Description
These bits indicate the status of the eight general purpose
event signals events to the SB
This bit indicates the status of the legacy power management
logic implemented inside the SB.
This bit indicates the Temperature Caution input.
This bit indicates the PME# from the internal USB controller
This bit indicates the PME# from the internal ac97 controller
This bit indicates the status of OtherTherm from NB, fan, etc.
This bit indicates the status of GPM[9] to SCI/Wakeup
This bit indicates the status of PCIeHotPlug
This bit indicates the status of ExtEvent0 to SCI/Wakeup
This bit indicates the status of ExtEvent1 to SCI/Wakeup
This bit indicates the PME# from PCIExpress
This bit indicates the status of GPM[0] to SCI/Wakeup
This bit indicates the status of GPM[1] to SCI/Wakeup
This bit indicates the status of GPM[2] to SCI/Wakeup
This bit indicates the status of GPM[3] to SCI/Wakeup
This bit indicates the status of GPM[8] to SCI/Wakeup
This bit indicates the status of GPIO0 (or WAKE#/GEVENT8
pin if PM IO Reg 84h bit1 =1) to SCI/wakeup
This bit indicates the status of GPM[4] to SCI/Wakeup
This bit indicates the status of GPM[5] to SCI/Wakeup
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary Page 178