AMD SB600 Technical Reference Manual page 161

Field Name
SwitchVoltageTime
Reserved
SwitchVoltageTime register
Field Name
SwitchGhiTime
Reserved
SwitchGHITime register
Field Name
UsbPhyS5PwrDwnEnable
Reserved
UsbResumeEnable
Reserved
UsbResetByPciRstEnable
UsbS5ResetEnable
Reserved
SpecialFunc
UsbPMControl register
Field Name
UsbBusyBreakEn
(available after A13)
UsbOhciCstateMask
(available after A13)
Reserved
K8KbRstEn
UsbBusyBmStsEn
UsbOhciBmStsRdEn
(available after A13)
MiscEnable66 register
Field Name
CPU_STP_En
Slp_En
CC_En
Reserved
BypassPwrGoodEn
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SwitchVoltageTime - RW – 8 bits - [PM_Reg: 63h]
Bits Default
5:0 05h Programmable value (in 2us increment with 2us uncertainty)
7:6 00b
SwitchGHI_Time - RW – 8 bits - [PM_Reg: 64h]
Bits Default
5:0 02h Programmable value (in 2us increment with 2us uncertainty)
7:6 00b
UsbPMControl- RW – 8 bits - [PM_Reg: 65h]
Bits Default
0 0b Set to 1 to enable S4/S5 USB Phy power down support and to
disable S4 USB wakeup support.
The bit has to be clear to 0 (default) to support S4 USB
wakeup.
1 0b
2 1b Set to 1 to enable S3 wakeup on USB device resume
3 0b
1b Set to 1 to reset USB on the software (such as IO-64 or IO-
4
CF9 cycles) generated PCIRST#.
5 1b Set to 1 to enable USB reset on S4/S5 resume detection
6 0b
7 0b If set to 1, S* -> S0 state transitions will use 1ms clock for
timing sequence; otherwise, 8µs clock will be used.
For K8 system, this bit must be cleared to use 8µs clock.
MiscEnable66 - RW – 8 bits - [PM_Reg: 66h]
Bits Default
Setting this bit to 1 will cause C3/4 wakeup when USB OHCI
0 0b
or EHCI DMA is active.
Setting this bit to 1 will prevent the system from entering C
1 0b
state when USB OHCI DMA is active.
4:2 000b
KB_RST# control for K8 system
5 0b 0: Generate INIT#
1: Generate PCIRST#
0b Setting this bit to 1 will cause C3/4 pop-up when USB OHCI or
6
EHCI DMA is active.
Setting this bit to 1 will keep BM_STS read as 1 regardless of
7 0b
BmStsRdMask when USB OHCI DMA is active.
MiscEnable67 – RW – 8 bits – [PM_Reg:67h]
Bits Default
CPU_STP# enable for C3 state in P4 system; no effect in K8
0 0b
systems, for which CPU_STP# is always deasserted.
1 0b SLP# enable in C states
2 0b C State enable; must be set in order to exercise C state
3
4 0b If asserted, Southbridge will not wait for deassertion of
PWRGOOD to monitor for wakeup event
Description
Description
Description
Description
Description
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary Page 161