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Field Name
Reserved
Debug Port Number
Reserved
Field Name
64-bit Addressing
Capability
Programmable Frame List
Flag
Asynchronous Schedule
Park Capability
Reserved
Isochronous Scheduling
Threshold
EHCI Extended
Capabilities Pointer (EECP)
Reserved
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
HCSPARAMS – R - 32 bits - [MEM_Reg : 04h]
Bits
Default
19:17
These bits are reserved and should be set to zero.
23:20
1h
Optional. This register identifies which of the host controller
ports is the debug port. The value is the port number (one-
based) of the debug port. A non-zero value in this field
indicates the presence of a debug port. The value in this
register must not be greater than N_PORTS.
31:24
These bits are reserved and should be set to zero.
HCCPARAMS – R - 32 bits - [MEM_Reg : 08h]
Bits
Default
0
0b
This field documents the addressing range capability of this
implementation.
0 = Data structures using 32-bit address memory pointers
1 = Data structures using 64-bit address memory pointers
1
1b
If this bit is set to a zero, then system software must use a
frame list length of 1024 elements with this host controller.
The USBCMD register Frame List Size field is a read-only
register and should be set to zero. If set to a one, then
system software can specify and use a smaller frame list
and configure the host controller via the USBCMD register
Frame List Size field. The frame list must always be aligned
on a 4K page boundary. This requirement ensures that the
frame list is always physically contiguous.
2
0b
If this bit is set to a one, then the host controller supports the
park feature for high-speed queue heads in the
Asynchronous Schedule. The feature can be disabled or
enabled and set to a specific level by using the
Asynchronous Schedule Park Mode Enable and
Asynchronous Schedule Park Mode Count fields in the
USBCMD register.
3
These bits are reserved and should be set to zero.
7:4
1h
This field indicates, relative to the current position of the
executing host controller, where software can reliably
update the isochronous schedule. When bit [7] is zero, the
value of the least significant 3 bits indicates the number of
micro-frames a host controller can hold a set of isochronous
data structures (one or more) before flushing the state.
When bit [7] is a one, then host software assumes the host
controller may cache an isochronous data structure for an
entire frame.
15:8
A0h
This optional field indicates the existence of a capabilities
list. A value of 00h indicates no extended capabilities are
implemented. A non-zero value in this register indicates the
offset in PCI configuration space of the first EHCI extended
capability. The pointer value must be 40h or greater if
implemented to maintain the consistency of the PCI header
defined for this class of device.
31:16
These bits are reserved and should be set to zero.
Description
Description
OCHI USB 1.1 and EHCI USB 2.0 Controllers
Proprietary
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