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AMD Geode SC1200 Data Book

AMD Geode SC1200 Data Book

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AMD Geode™ SC1200/SC1201
Processor Data Book
March 2006
Publication ID: 32579B
AMD Geode™ SC1200/SC1201 Processor Data Book

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Summary of Contents for AMD Geode SC1200

  • Page 1 AMD Geode™ SC1200/SC1201 Processor Data Book March 2006 Publication ID: 32579B AMD Geode™ SC1200/SC1201 Processor Data Book...
  • Page 2 Contacts www.amd.com Trademarks AMD, the AMD Arrow logo, and combinations thereof, and Geode, and Virtual System Architecture are trademarks of Advanced Micro Devices, Inc. Microsoft and Windows are registered trademarks of Microsoft Corporation in the United States and/or other jurisdictions.

  • Page 3: Table Of Contents

    Legacy Functional Blocks ........... . 129 AMD Geode™ SC1200/SC1201 Processor Data Book...
  • Page 4 Data Book Revision History ..........442 AMD Geode™ SC1200/SC1201 Processor Data Book...

  • Page 5: List Of Figures

    Figure 7-5. Capture Video Mode Bob Example Using One Video Frame Buffer ....317 AMD Geode™ SC1200/SC1201 Processor Data Book 32579B List of Figures...
  • Page 6 Figure 9-44. Standard Parallel Port Typical Data Exchange Timing Diagram ..... 423 List of Figures AMD Geode™ SC1200/SC1201 Processor Data Book...
  • Page 7 BGU481 Package - Bottom View ..........440 AMD Geode™ SC1200/SC1201 Processor Data Book...
  • Page 8 32579B List of Figures AMD Geode™ SC1200/SC1201 Processor Data Book...

  • Page 9: List Of Tables

    Table 5-28. Bank 1 - CEIR Wakeup Configuration and Control Register Map ....117 AMD Geode™ SC1200/SC1201 Processor Data Book 32579B...
  • Page 10 F2BAR4: IDE Controller Support Registers Summary ......183 List of Tables AMD Geode™ SC1200/SC1201 Processor Data Book...
  • Page 11 TFT Timing Parameters ........... . 382 Table 9-16. CRT VESA Compatible DAC (RED, GREEN, and BLUE Outputs) ....383 AMD Geode™ SC1200/SC1201 Processor Data Book 32579B...
  • Page 12 Revision History ............442 List of Tables AMD Geode™ SC1200/SC1201 Processor Data Book...

  • Page 13: General Description

    Overview General Description The AMD Geode™ SC1200 and SC1201 processors are members of the AMD Geode processor family of fully inte- grated x86 system chips. The SC1200/SC1201 processor includes: • The Geode GX1 processor module combines advanced CPU performance with MMX™ support, fully acceler-...

  • Page 14: Features

    — Composite, S-Video and YCrCb component video outputs — Analog video output interface supports SCART stan- dard (both RGBCvbs and YCCvbs) — Support for VBI (Vertical Blanking Interval) transfer from Video Port input to TV Encoder AMD Geode™ SC1200/SC1201 Processor Data Book Overview...
  • Page 15 — 8-Bit (optional 16-bit) data bus width — Shares balls with PCI signals — Is not a subtractive agent AMD Geode™ SC1200/SC1201 Processor Data Book 32579B ■ IDE Interface: — Two IDE channels for up to four external IDE devices —...
  • Page 16 32579B Overview AMD Geode™ SC1200/SC1201 Processor Data Book...

  • Page 17: Gx1 Module

    The GX1 processor (silicon revision 8.1.1) is the central module of the SC1200/SC1201 processor. For detailed information regarding the GX1 module, refer to the AMD Geode™ GX1 Processor Data Book and the AMD Geode™ GX1 Processor Silicon Revision 8.1.1 Specifica- tion Update documents.

  • Page 18: Table 2-1. Sc1200/Sc1201 Processor Memory Controller Register Summary

    MC_DR_ADD. Memory Controller Dirty RAM Address Register MC_DR_ACC. Memory Controller Dirty RAM Access Register MC_MEM_CNTRL1 (R/W) 100: ÷ 3.5 101: ÷ 4 110: ÷ 4.5 111: ÷ 5 AMD Geode™ SC1200/SC1201 Processor Data Book Architecture Overview Reset Value 248C0040h 00000801h 41104110h 2A733225h 00000000h 00000000h...
  • Page 19 1: 2 Core clocks. FSTRDMSK (Fast Read Mask). Do not allow core reads to bypass the request FIFO. 0: Disable. 1: Enable. AMD Geode™ SC1200/SC1201 Processor Data Book MC_MEM_CNTRL2 (R/W) 100: Shift 2 core clocks 101: Shift 2.5 core clocks...
  • Page 20 1111: 16 CLK 100: 4 CLK 110: 6 CLK 101: 5 CLK 111: 7 CLK 100: 4 CLK 110: 6 CLK 101: 5 CLK 111: 7 CLK AMD Geode™ SC1200/SC1201 Processor Data Book Architecture Overview Reset Value: 41104110h Reset Value: 2A733225h...
  • Page 21 31:2 RSVD (Reserved). Write as 0. D (Dirty Bit). This bit is read/write accessible. V (Valid Bit). This bit is read/write accessible. AMD Geode™ SC1200/SC1201 Processor Data Book 100: 4 CLK 110: 6 CLK 101: 5 CLK 111: 7 CLK...

  • Page 22: Video Processor Module

    8-bit bus, at the Video Processor. For more information about the GX1 module’s interface to the Video Processor, see the “Display Controller” chapter in the AMD Geode™ GX1 Processor Data Book. Video Processor Module The Video Processor provides high resolution and graphics for a CRT, TV, or TFT/DSTN interface.

  • Page 23: Superi/O Module

    • CPU_RST resets the CPU and is asserted for approxi- mately 100 µs after the negation of POR#. • PCI bus interface signals. AMD Geode™ SC1200/SC1201 Processor Data Book 32579B SuperI/O Module The SuperI/O (SIO) module is a PC98 and ACPI compliant SIO that offers a single-cell solution to the most commonly used ISA peripherals.
  • Page 24 32579B Architecture Overview AMD Geode™ SC1200/SC1201 Processor Data Book...

  • Page 25: 3.0Signal Definitions

    Straps are not the default signal, shown with system signals for reader convenience. However, also listed in figure with the appropriate functional group. AMD Geode™ SC1200/SC1201 Processor Data Book 3.0Signal Definitions listed first and is separated by a plus sign (+). A slash (/) in a signal name means that the function is always enabled and available (i.e., cycle multiplexed).
  • Page 26 Signal Groups (Continued) • Section 3.3 "Multiplexing Configuration": Lists multi- plexing options and their configurations. • Section 3.4 "Signal Descriptions": Detailed descriptions of each signal according to functional group. AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definitions PCICLK INTA#, INTB# FRAME#...

  • Page 27: Ball Assignments

    Pin Multiplexing Register (PMR). See Section 4.2 "Pin Multiplexing, Interrupt Selection, and Base Address Registers" on page 72 for a detailed description of this register. AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Table 3-1. Signal Definitions Legend Mnemonic...

  • Page 28: Figure 3-2. Bgu481 Ball Assignment Diagram

    MD35 MD46 MD43 DQM5 V MD4 DQM0 CS0# MA0 DQM4 V MD38 MD39 MD44 MD40 CKEA MA7 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definitions STB# CVBS SVY TVRST D+P3 D-P3 D+P1 D-P1 TVIOM AV TVCMP D+P2 D-P2 GP10 SSTV...

  • Page 29: Table 3-2. Bgu481 Ball Assignment - Sorted By Ball Number

    22.5 IOCS0# 22.5 TFTDCK 22.5 HSYNC CCCRT GREEN WIRE BLUE WIRE PLL2 AMD Geode™ SC1200/SC1201 Processor Data Book Power Ball Rail Configuration Signal Name 6, 2 Cycle Multiplexed TFTD13 F_AD7 Strap (See Table 3- 4 on page 44.) 6, 2...
  • Page 30 PMR[15] = 1) and (PMR[27] = 0 and FPCI_MON = 0) DSR2# PMR[23] = 0 and (PMR[27] = 1 or IDE_IORDY1 FPCI_MON = 1) SDTEST1 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definitions Buffer Power (PU/PD) Type Rail Configuration PMR[23] = 0 and...
  • Page 31 IRTX SOUT3 SSCRT CCCRT SSCRT SSCRT SSPLL2 SLCT TFTD15 F_C/BE3# 14/14 TFTD10 F_AD4 14/14 AMD Geode™ SC1200/SC1201 Processor Data Book Power Ball Rail Configuration Signal Name Cycle Multiplexed TFTD11 Cycle Multiplexed F_AD5 Cycle Multiplexed TFTD9 F_AD3 Strap (See Table 3- 4 on page 44.)
  • Page 32 = 0 and PMR[13] = 1) or (PMR[23] = 1 and PMR[15] = 1 and PMR[13] = 1) PMR[23] = 1 and PMR[15] = 0 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definitions Buffer Power (PU/PD) Type Rail Configuration PMR[12] = 0 PMR[12] = 1 22.5...
  • Page 33 WIRE AD16 AD19 AD18 DEVSEL# 22.5 BHE# SIN2 SDTEST3 TRST# 22.5 22.5 AMD Geode™ SC1200/SC1201 Processor Data Book Power Ball Rail Configuration Signal Name TRDY# PMR[23] = 0 and (PMR[27] = 0 and FPCI_MON = 0) PMR[23] = 1 and...
  • Page 34 = 1 and PMR[22] PMR[14] = 0 and PMR[22] PMR[14] = 1 and PMR[22] Cycle Multiplexed Cycle Multiplexed CORE CORE AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definitions Buffer Power (PU/PD) Type Rail Configuration Cycle Multiplexed Cycle Multiplexed PMR[14] = 0 and 22.5...
  • Page 35 CORE CORE SDATA_OUT AC97 TFT_PRSNT STRP SYNC AC97 CLKSEL3 STRP AC97_CLK AMD Geode™ SC1200/SC1201 Processor Data Book Power Ball Rail Configuration Signal Name PMR[19] = 0 PMR[19] = 1 PMR[23] = 0 or (PMR[23] = 1 and PMR[15] = 1)
  • Page 36 PMR[24] = 1 PMR[24] = 0 PMR[24] = 1 IDE_DATA3 TFTD12 MD24 AB28 AB29 AB30 AB31 DQM7 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definitions Buffer Power (PU/PD) Type Rail Configuration , TS PMR[24] = 0 PMR[24] = 1 PMR[24] = 0...
  • Page 37 MD50 , TS AF28 MD49 , TS AF29 MD54 , TS AF30 MD53 , TS AF31 AMD Geode™ SC1200/SC1201 Processor Data Book Power Ball Rail Configuration Signal Name PMR[24] = 0 GPIO18 PMR[24] = 1 DTR1#/BOUT1 PMR[24] = 0 SIN1...
  • Page 38 AL17 MD39 AL18 AL19 MD44 AL20 MD40 AL21 PMR[6] = 0 AL22 CKEA PMR[6] =1 AL23 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definitions Buffer Power (PU/PD) Type Rail Configuration , TS , TS , TS , TS , TS...
  • Page 39 May need 5V tolerant protection at system level (DDC_SCL, DDC_SDA). Is back-drive protected (MD[63:0], DPOS_PORT1, DNEG_PORT1, DPOS_PORT2, DNEG_PORT2, DPOS_PORT3, DNEG_PORT3, ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#, PD[7:0], PE, SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#, PWRCNT[2:1]). AMD Geode™ SC1200/SC1201 Processor Data Book Power Rail Configuration 32579B...

  • Page 40: Table 3-3. Bgu481 Ball Assignment - Sorted Alphabetically By Signal Name

    CLK27M CLK32 CLKSEL0 CLKSEL1 CLKSEL2 CLKSEL3 C23, D24 CS0# AL12 CS1# AH27 CTS2# CVBS A23, A24, D24 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definitions Signal Name Ball No. DCD2# DDC_SCL DDC_SDA DEVSEL# DID0 DID1 DNEG_PORT1 DNEG_PORT2 DNEG_PORT3 DOCCS# A9, N31...
  • Page 41 GPIO20 A9, N31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38/IRRX2 GPIO39 GPIO40 GPIO41 GPWIO0 GPWIO1 GPWIO2 GREEN AMD Geode™ SC1200/SC1201 Processor Data Book Signal Name Ball No. GTEST GXCLK HSYNC IDE_ADDR0 IDE_ADDR1 IDE_ADDR2 IDE_CS0# IDE_CS1# IDE_DACK0# IDE_DACK1# IDE_DATA0 IDE_DATA1 IDE_DATA2...
  • Page 42 AA28 SDCLK3 SDTEST0 SDTEST1 SDTEST2 SDTEST3 SDTEST4 SDTEST5 SERIRQ SERR# SETRES SIN1 SIN2 SIN3 SLCT SLIN#/ASTRB# AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definitions Signal Name Ball No. SMI_O SOUT1 SOUT2 SOUT3 STB#/WRITE# STOP# SYNC TEST0 TEST1 TEST2 TEST3 TFT_PRSNT...
  • Page 43 AK13, AK16, AK19, AK31, AL2, AL30, VOPCK VOPD0 VOPD1 VOPD2 VOPD3 VOPD4 VOPD5 VOPD6 VOPD7 VPCKIN VPD0 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Name Ball No. VPD1 VPD2 VPD3 VPD4 VPD5 VPD6 VPD7 VPLL2 VPLL3 VREF 32579B Signal Name Ball No.

  • Page 44: Strap Options

    Note: Accuracy of internal PU/PD resistors: 80K to 250K. Location of the GCB (General Configuration Block) cannot be determined by software. See the AMD Geode™ SC1200/SC1201 Processor Specification Update document. PU or PD resistor with a value of 1.5 KΩ be placed on the balls listed in Table 3-4.

  • Page 45: Multiplexing Configuration

    IDE_RST# IRQ14 Sub-ISA TRDE# AMD Geode™ SC1200/SC1201 Processor Data Book system reset, the pull-up is present. This pull-up resistor can be disabled by writing Core Logic registers. The config- uration is without regard to the selected ball function. The above applies to all pins multiplexed with GPIO, except GPIO12, GPIO13, and GPIO16.
  • Page 46 PMR[28] = 0 SDTEST3 AC97 FPCI_MON = 0 F_STOP# F_GNT0# F_TRDY# PMR[29] = 0 TEST1 TEST2 TEST0 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definitions Alternate Signal Configuration ACCESS.bus PMR[19] = 1 UART PMR[16] = 1 UART PMR[6] = 1...

  • Page 47: Table 3-6. Three-Signal/Group Multiplexing

    The combination of PMR[9] = 1 and PMR[4] = 0 is undefined and should not be used. These TFT outputs are reset to 0 by POR# if the TFT_PRSNT strap is pulled high or PMR[10] = 0. This relates to signals TFTD[17:0], TFTDE, TFTDCK. AMD Geode™ SC1200/SC1201 Processor Data Book Alternate1 Signal...

  • Page 48: Table 3-7. Four-Signal/Group Multiplexing

    VOPD2 VOPD3 VOPD4 VOPD5 VOPD6 VOPD7 VOPD0 PMR[23] = 1 (PMR[27] = 0 and FPCI_MON = 0) AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definitions Alternate3 Configuration Signal Configuration IDE2 Internal Test PMR[17] = 0 and SDTEST0 PMR[17] = 1 and...

  • Page 49: Signal Descriptions

    BOOT16 LPC_ROM TFT_PRSNT FPCI_MON DID1 DID0 POR# AMD Geode™ SC1200/SC1201 Processor Data Book Description Fast-PCI Clock Selects. These strap signals are used to set the internal Fast-PCI clock. 00 = 33.3 MHz 01 = 48 MHz 10 = 66.7 MHz 11 = 33.3 MHz...

  • Page 50: Memory Interface Signals

    SDRAM commands. CASA# is used with CS[1:0]#. Write Enable. RAS#, CAS#, WE# and CKE are encoded to support the different SDRAM commands. WEA# is used with CS[1:0]#. AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definitions IDE_DATA5...
  • Page 51 VPD3 VPD2 VPD1 VPD0 VPCKIN AMD Geode™ SC1200/SC1201 Processor Data Book Description Data Mask Control Bits. During memory read cycles, these outputs control whether SDRAM output buffers are driven on the MD bus or not. All DQM signals are asserted during read cycles.
  • Page 52 Set Resistor. This signal sets the current level for the RED/GREEN/BLUE analog outputs. Typically, a 464 Ω, 1% resistor is connected between this ball and AV Analog Red, Green and Blue AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definitions PD2+TFTD8+ F_AD2...
  • Page 53 TFTDE FP_VDD_ON TFTD[17:0] Table 3-3 on page AMD Geode™ SC1200/SC1201 Processor Data Book Description TFT Clock. Clock to external CRT DACs or TFT. TFT Data Enable. Can be used as blank signal to exter- nal CRT DACs. TFT Power Control. Used to enable power to the Flat Panel display, with power sequence timing.
  • Page 54 75 Ω trans- mission line. TV Output Dump Current. Typically, a 9.3 Ω, 1% resistor is connected between this ball and AV AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definitions See F4BAR0+ Memory Offset...

  • Page 55: Pci Bus Interface Signals

    Table 3-3 AD[23:0] on page C/BE3# C/BE2# C/BE1# C/BE0# AMD Geode™ SC1200/SC1201 Processor Data Book Description ACCESS.bus 1 Serial Clock. This is the serial clock for the interface. Note: If selected as AB1C function but not used, tie AB1C high.
  • Page 56 AD[31:0]. During a write, it indicates that the target is prepared to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. This signal is internally connected to a pull-up resistor. AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definitions GPIO19+IOCHRDY IDE_DATA7...
  • Page 57 Type STOP# LOCK# DEVSEL# AMD Geode™ SC1200/SC1201 Processor Data Book Description Target Stop. STOP# is asserted to indicate that the cur- rent target is requesting that the master stop the current transaction. This signal is used with DEVSEL# to indicate retry, disconnect, or target abort.
  • Page 58 Each of these signals is internally connected to a pull-up resistor. GNT0# must have a pull-down resistor of 1.5 KΩ, GNT1# must have a pull-down resistor of 1.5 KΩ. AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definitions DID1 (Strap) DID0 (Strap)
  • Page 59 TRDE# IOR# IOW# DOCR# DOCW# IRQ9 IOCHRDY AMD Geode™ SC1200/SC1201 Processor Data Book Description Address Lines Data Bus Byte High Enable. With A0, defines byte accessed for 16 bit wide bus cycles. I/O Chip Selects ROM or Flash ROM Chip Select DiskOnChip or NAND Flash Chip Select Transceiver Data Enable Control.
  • Page 60 Serial IRQ. The interrupt requests are serialized over a single signal, where each IRQ level is delivered during a designated time slot. Note: If SERIRQ function is selected but not used, tie SERIRQ high. AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definitions GPIO35 GPIO34 GPIO33 GPIO32...

  • Page 61: Table 6-44. Dma

    IDE_DREQ1 IDE_DACK0# IDE_DACK1# IRQ14 IRQ15 AMD Geode™ SC1200/SC1201 Processor Data Book Description IDE Reset. This signal resets all devices attached to the IDE interface. IDE Address Bits. These address bits are used to access a register or data port in a device on the IDE bus.
  • Page 62 Baud Outputs. Provide the associated serial channel baud rate generator output signal if test mode is selected (i.e., bit 7 of the EXCR1 Register is set). AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definitions SDTEST3 IRRX1 CLKSEL1 (Strap)
  • Page 63 ACK# AFD#/DSTRB# BUSY/WAIT# ERR# INIT# AMD Geode™ SC1200/SC1201 Processor Data Book Description Ring Indicator. When low, indicates to the modem that a telephone ring signal has been received by the modem. They are monitored during power-off for wakeup event detection.
  • Page 64 This input signal can be used when GPIO38 is selected using PMR[14], and when AUX_IRRX bit in register IRCR2 of the IR module in internal SuperI/O is set. IR Transmit. IR serial output data. AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definitions TFTD13+F_AD7 TFTD1+VOPD0+ F_AD6...

  • Page 65: Power Management Interface Signals

    CLK32 GPWIO0 GPWIO1 GPWIO2 LED# ONCTL# AMD Geode™ SC1200/SC1201 Processor Data Book Description Audio Bit Clock. The serial bit clock from the codec. Note: If selected as BIT_CLK function but not used, tie BIT_CLK low. Serial Data Output. This output transmits audio serial data to the codec.
  • Page 66 Suspend Power Plane Control 1 and 2. Control signal asserted during power management Suspend states. These signals are open-drain outputs. Thermal Event. Active low signal generated by external hardware indicating that the system temperature is too high. AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definitions...

  • Page 67: Gpio Interface Signals

    GPIO37 GPIO38/IRRX2 GPIO39 GPIO40 GPIO41 AMD Geode™ SC1200/SC1201 Processor Data Book Description GPIO Port 0. Each signal is configured independently as an input or I/O, with or without static pull-up, and with either open-drain or totem-pole output type. A debouncer and an interrupt can be enabled or masked for each of signals GPIO[00:01] and [06:15] indepen- dently.

  • Page 68: Jtag Interface Signals

    To enable, pull up FPCI_MON (ball A4). Description JTAG Test Clock. This signal has an internal weak pull-up resistor. JTAG Test Data Input. This signal has an internal weak pull-up resistor. AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definitions ACK#+TFTDE+ VOPCK PD7+TFTD13 PD6+TFTD1+...
  • Page 69 SDTEST5 SDTEST4 SDTEST3 SDTEST2 SDTEST1 SDTEST0 AMD Geode™ SC1200/SC1201 Processor Data Book Description JTAG Test Data Output JTAG Test Mode Select. This signal has an internal weak pull-up resistor. JTAG Test Reset. This signal has an internal weak pull-up resistor.

  • Page 70: Power And Ground Connections

    This signal requires a 0.1 μF bypass capacitor to V . This supply must be present when V 1.8V Core Processor Power Connections. 3.3V I/O Power Connections. Ground Connections. AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definitions to V is present.

  • Page 71: 4.0General Configuration Block

    General Configuration block registers. All subsequent writes to this address, are ignored until system reset. Note: Location of the General Configuration Block cannot be determined by software. See the AMD Geode™ SC1200/SC1201 Processor Specification Update document. Reserved bits in the General Configuration block should be read as written unless otherwise specified.

  • Page 72: Pin Multiplexing, Interrupt Selection, And Base Address Registers

    SLCT+TFTD15 PE+TFTD14 BUSY/WAIT#+TFTD3+VOPD2 ERR#+TFTD4+VOPD3 STB#/WRITE#+TFTD7 SLIN#/ASTRB#+TFTD16 AFD#/DSTRB#+TFTD2+VOPD1 INIT#+TFTD5+VOPD4 GPIO16+PC_BEEP AC97_RST# SDATA_IN BIT_CLK AMD Geode™ SC1200/SC1201 Processor Data Book General Configuration Block Reset Value: 00000000h Add’l Dependencies None None None PMR[23] = 0 Add’l Dependencies See Note. Add’l Dependencies See PMR[23]...
  • Page 73 C24 / AC4 IDE_DREQ0 C25 / AD4 IDE_DACK0# A22 / AA1 IDE_RST# A25 / AD1 IDE_IORDY0 D25 / AF1 IRQ14 AMD Geode™ SC1200/SC1201 Processor Data Book 32579B 1: CRT, GPIO and TFT Signals Name TFTD3 TFTD2 TFTD4 TFTD6 TFTD16 TFTD14...
  • Page 74 IOCS1# AB1D PMR[29] = 0 FP_VDD_ON PMR[29] = 1 GXCLK AMD Geode™ SC1200/SC1201 Processor Data Book General Configuration Block Add’l Dependencies PMR[15] = 0 PMR[15] = 1 and PMR[13] = 0 PMR[15] = 1 and PMR[13] = 1 PMR[15] = 0...
  • Page 75 GPIO38/IRRX2 AL8 / J31 GPIO39 IOCS1SEL (Select IOCS1). Selects ball functions for IOCS1# or GPIO1. Works in conjunction with PMR[23], see PMR[23] for definition. AMD Geode™ SC1200/SC1201 Processor Data Book 1: GPIO Signals Add’l Dependencies Name PMR[2] = 0 GPIO14...
  • Page 76 None SOUT3 1: Audio Signal Add’l Dependencies Name FPCI_MON = 0 PC_BEEP FPCI_MON = 1 F_DEVSEL# AMD Geode™ SC1200/SC1201 Processor Data Book General Configuration Block Add’l Dependencies None Add’l Dependencies PMR[4] = 1 PMR[4] = 0 Add’l Dependencies None None Add’l Dependencies...
  • Page 77 1: 16-bit wide DOCCS# access is used. Reserved. Write as read. IRTXEN (Infrared Transmitter Enable). This bit enables drive of Infrared transmitter output. 0: IRTX+SOUT3 line (ball C11) is HiZ. 1: IRTX+SOUT3 line (ball C11) is enabled. AMD Geode™ SC1200/SC1201 Processor Data Book 32579B...
  • Page 78 Device Identification Number Register - ID (RO) This register identifies the device. SC1200 = 04h. SC1201 = 05h. Offset 3Dh This register identifies the device revision. See the AMD Geode™ SC1200/SC1201 Processor Specification Update document for value. Offset 3Eh-3Fh Configuration Base Address Register - CBA (RO) This register sets the base address of the Configuration block.

  • Page 79: Watchdog

    SUSPA# 32 KHz WDPRES POR# AMD Geode™ SC1200/SC1201 Processor Data Book • The GX1 module’s internal SUSPA# signal is 1. • The GX1 module’s internal SUSPA# signal is 0 and the WD32KPD bit (Offset 02h[8]) is 0. The 32 KHz input clock is disabled, when: •...

  • Page 80: Table 4-3. Watchdog Registers

    Table 4-3. WATCHDOG Registers WATCHDOG Timeout Register - WDTO (R/W) 1000: 256 1100: 4096 1001: 512 1101: 8192 1010: 1024 1110: Reserved 1011: 2048 1111: Reserved AMD Geode™ SC1200/SC1201 Processor Data Book General Configuration Block Reset Value: 0000h Reset Value: 0000h...

  • Page 81: High-Resolution Timer

    SUSPA# signal is 0 and the TM27MPD bit is 1. For more information about signal SUSPA# see Section 4.4.2.1 "Usage Hints" on page 81 and the AMD Geode™ GX1 Processor Data Book. The High-Resolution Timer function resides on the internal Fast-PCI bus and its registers are in General Configuration Block address space.

  • Page 82: Table 4-4. High-Resolution Timer Registers

    1: High-Resolution Timer interrupt is enabled. Offset 0Eh-0Fh TIMER Value Register - TMVALUE (RO) TIMER Status Register - TMSTS (R/W) Reserved - RSVD AMD Geode™ SC1200/SC1201 Processor Data Book General Configuration Block Reset Value: xxxxxxxxh Reset Value: 00h Reset Value: 00h...

  • Page 83: Clock Generators And Plls

    PLL2 and PLL5. V PLL2 Figure 4-2. Clock Generation Block Diagram AMD Geode™ SC1200/SC1201 Processor Data Book The clock generators are based on 32.768 KHz and 27.000 MHz crystal oscillators. The 32.768 KHz crystal oscillator is described in Section 5.5.2 "RTC Clock Generation" on page 105 (functional description of the RTC).

  • Page 84: Figure 4-3. Recommended Oscillator External Circuitry

    27.00 MHz Parallel mode AT-cut or BT-cut 40 Ω 7 pF 10-20 pF User-defined 20 MΩ 100 Ω 3-24 pF 3-24 pF AMD Geode™ SC1200/SC1201 Processor Data Book General Configuration Block To other modules Internal External X27I X27O Circuitry Tolerance...

  • Page 85: Table 4-6. Core Clock Frequency

    0110 66.67 1010 Note: Not all speeds are supported. For information on supported speeds, see Section A.1 "Order Information" on page 441. AMD Geode™ SC1200/SC1201 Processor Data Book Table 4-6. Core Clock Frequency Internal Fast-PCI Clock Freq. (MHz) Multiplier Value 33.33...
  • Page 86 (Capture Video mode), the video clock is generated by the Display Controller. • If the video data is coming directly from the VIP block (Direct Video mode), the Video Clock is generated by the VIP block. AMD Geode™ SC1200/SC1201 Processor Data Book...

  • Page 87: Table 4-8. Clock Generator Configuration

    MOC (MO Counter Value). Fvco = OSCCLK * MFBC / (MFFC * MOC) OSCCLK = 27 MHz AMD Geode™ SC1200/SC1201 Processor Data Book Reserved - RSVD PLL Power Control Register - PPCR (R/W) Reserved - RSVD PLL3 Configuration Register - PLL3C (R/W)
  • Page 88 0100: Multiply by 4 0101: Multiply by 5 0110: Multiply by 6 0111: Multiply by 7 1000: Multiply by 8 1001: Multiply by 9 1010: Multiply by 10 Other: Reserved General Configuration Block Reset Value: Strapped Value AMD Geode™ SC1200/SC1201 Processor Data Book...

  • Page 89: 5.0Superi/O Module

    Serial Port 2 System Wakeup Control Wakeup PWUREQ Events AMD Geode™ SC1200/SC1201 Processor Data Book 5.0SuperI/O Module Outstanding Features • Full compatibility with ACPI Revision 1.0 requirements. • System Wakeup Control powered by V power-up request and a PME (power management...

  • Page 90: Features

    • Y2K Compliant Clock Sources • 48 MHz clock input • On-chip low frequency clock generator for wakeup • 32.768 KHz crystal with an internal frequency multiplier to generate all required internal frequencies AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module...

  • Page 91: Module Architecture

    AB2D Real-Time Clock (RTC) Internal Signal AMD Geode™ SC1200/SC1201 Processor Data Book The central configuration register set supports ACPI com- pliant PnP configuration. The configuration registers are structured as a subset of the Plug and Play Standard Reg- isters, defined in Appendix A of the Plug and Play ISA Specification Version 1.0a by Intel and Microsoft.

  • Page 92: Configuration Structure / Access

    LDN register. Logical Device Number Register Logical Device Control Register Banks (One per Logical Device) Figure 5-3. Standard Configuration Register File AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module Reference Page 98 Page 100 Page 101 Page 102...

  • Page 93: Address Decoding

    • When either a hardware or a software reset occurs: — The legacy devices are assigned with their legacy system resource allocation. — The AMD proprietary functions are not assigned with any default resources and the default values of their base addresses are all 00h.

  • Page 94: Standard Configuration Registers

    DMA Channel Select 0 DMA Channel Select 1 Device Specific Logical Device Configuration 1 Device Specific Logical Device Configuration 2 Device Specific Logical Device Configuration 3 Device Specific Logical Device Configuration 4 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module...

  • Page 95: Table 5-3. Standard Configuration Registers

    The valid choices are 0-3, where a value of 0 selects DMA channel 0, 1 selects channel 1, etc. A value of 4 indicates that no DMA channel is active. Values 5-7 are reserved. AMD Geode™ SC1200/SC1201 Processor Data Book write to prevent the values of reserved bits from being changed during write.
  • Page 96 The valid choices are 0-3, where a value of 0 selects DMA channel 0, 1 selects channel 1, etc. A value of 4 indicates that no DMA channel is active. Values 5-7 are reserved. Index F0h-FEh Special (vendor-defined) configuration options. DMA Channel Select 1 (R/W) Logical Device Configuration (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module...

  • Page 97: Table 5-4. Sio Control And Configuration Register Map

    SID. SIO ID SIOCF1. SIO Configuration 1 SIOCF2. SIO Configuration 2 SRID. SIO Revision ID RSVD. Reserved exclusively for AMD use. Table 5-5. SIO Control and Configuration Registers Description Index 20h Chip ID. Contains the identity number of the module. The SIO module is identified by the value F5h.

  • Page 98: Table 5-6. Relevant Rtc Configuration Registers

    Real-Time Clock (RTC). Only the last registers (F0h-F3h) are described here (Table 5-7). See Table 5-3 "Standard Configuration Registers" on page 95 for descrip- tions of the other registers. AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module Reset Value...

  • Page 99: Table 5-7. Rtc Configuration Registers

    Month Alarm Register Offset Register - MANAO (R/W) Reserved. Month Alarm Register Offset Value. Index F3h Century Register Offset Register - CENO (R/W) Reserved. Century Register Offset Value. AMD Geode™ SC1200/SC1201 Processor Data Book Table 5-7. RTC Configuration Registers RAM Lock Register - RLR (R/W) 32579B...

  • Page 100: Table 5-8. Relevant Swc Registers

    The logical device registers are maintained, and all wakeup detection mechanisms are functional. described earlier in Table 5-3 "Standard Configuration Reg- isters" on page 95. Table 5-8. Relevant SWC Registers AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module Reset Value...

  • Page 101: Table 5-9. Relevant Ircp/Sp3 Registers

    0: Disabled. (Default) 1: Enabled (when the device is inactive). AMD Geode™ SC1200/SC1201 Processor Data Book Only the last register (F0h) is described here (Table 5-10). See Table 5-3 "Standard Configuration Registers" on page 95 for descriptions of the other registers listed.

  • Page 102: Table 5-11. Relevant Serial Ports 1 And 2 Registers

    Serial Ports 1 and 2. Only the last register (F0h) is described here (Table 5-12). See Table 5-3 "Standard Con- figuration Registers" on page 95 for descriptions of the oth- ers. AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module Reset Value Port 1...

  • Page 103: Table 5-13. Relevant Acb1 And Acb2 Registers

    0: No internal pull-up resistors on AB1C/AB2C and AB1D/AB2D. (Default) 1: Internal pull-up resistors on AB1C/AB2C and AB1D/AB2D. Reserved. AMD Geode™ SC1200/SC1201 Processor Data Book ACB1 is designated as LDN 05h and ACB2 as LDN 06h. Table 5-13 lists the configuration registers which affect the ACCESS.bus ports.

  • Page 104: Table 5-15. Relevant Parallel Port Registers

    Parallel Port. Only the last register (F0h) is described here (Table 5-16). See Table 5-3 "Standard Configuration Regis- ters" on page 95 for descriptions of the others. Parallel Port Configuration Register (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module Reset Value...

  • Page 105: Real-Time Clock (Rtc)

    (whether system is on or off). In systems where this is not the case, C and C should be different by 50% to assure an unbalanced circuit. AMD Geode™ SC1200/SC1201 Processor Data Book 5.5.2 RTC Clock Generation The RTC uses a 32.768 KHz clock signal as the basic clock for timekeeping.

  • Page 106: Figure 5-6. External Oscillator Connections

    See Table 5-20 on page 111 for more details. is higher than (3.0V). The SBMIN Battery Figure 5-6. External Oscillator Connections 32.768 KHz X32I Figure 5-7. Divider Chain Control AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module To other modules Internal External X32O CLKIN (X32I) 3.3V square wave...
  • Page 107 This mecha- nism enables new time parameters to be loaded in the RTC. AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Method 2 Access the RTC registers after detection of an Update Ended interrupt.

  • Page 108: Figure 5-8. Power Supply Connections

    0.50 μF 0.25 Note: Battery voltage in this test is 3.0V. Figure 5-11. Typical Battery Current: Normal AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module maintains the correct time and voltage is absent, main battery. voltage should be maintained above its (μA)

  • Page 109: Table 5-18. System Power States

    To protect the RTC internal regis- ters from corruption, all inputs are automatically locked out. The lockout condition is asserted when V SBON AMD Geode™ SC1200/SC1201 Processor Data Book Power-Up Detection When system power is restored after a power failure or power off state (V for a delay of 62 msec (minimum) to 125 msec (maximum) after the RTC switches from battery to system power.

  • Page 110: Figure 5-12. Interrupt/Status Timing

    128 bytes of battery-backed RAM (also called Extended RAM) may be accessed via a second pair of Index and Data registers. Access to the two RAMs may be locked. For details see Table 5-7 on page 99. AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module...

  • Page 111: Table 5-19. Rtc Register Map

    Index 02h Minutes Data. Values can be 00 to 59 in BCD format, or 00 to 3B in binary format. AMD Geode™ SC1200/SC1201 Processor Data Book Note: Before attempting to perform any start-up proce- dures, read about bit 7 (VRT) of the CRD Register.
  • Page 112 Month Register - MON (R/W) Year Register - YER (R/W) RTC Control Register A - CRA (R/W) RTC Control Register B - CRB (R/W) power-up reset only. AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module Reset Type: V Reset Type: V Reset Type: V...
  • Page 113 When bits 7 and 6 are both set to one (“11”), unconditional match is selected. (Default) Index Programmable Century Data. Values may be 00 to 99 in BCD format or 00 to 63 in Binary format. AMD Geode™ SC1200/SC1201 Processor Data Book Table 5-20. RTC Registers (Continued) power-up reset only.

  • Page 114: Table 5-21. Divider Chain Control / Test Selection

    81 to 92 (PM) 00 to 23 24-hour mode: 01 to 07 01 to 1F 01 to 0C 00 to 63 00 to 63 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module Periodic Interrupt Divider Rate (msec) Chain Output No interrupts 3.906250 7.812500...

  • Page 115: Table 5-24. Standard Ram Map

    The supercap capacitor in the range of 0.047- 0.47 F should supply the power during the battery replacement. AMD Geode™ SC1200/SC1201 Processor Data Book 32579B 5.5.4 RTC General-Purpose RAM Map Table 5-24.

  • Page 116: System Wakeup Control (Swc)

    Table 5-26 lists the recommended time ranges limits for the different protocols and their applicable ranges. The values are represented in hexadecimal code where the units are of 0.1 ms. Low Limit High Limit AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module Low Limit High Limit...

  • Page 117: Table 5-27. Banks 0 And 1 - Common Control And Status Register Map

    Table 5-28. Bank 1 - CEIR Wakeup Configuration and Control Register Map Offset Type AMD Geode™ SC1200/SC1201 Processor Data Book • Bank 0 holds reserved registers. • Bank 1 holds the CEIR Control Registers. The active bank is selected through the Configuration Bank Select field (bits [1:0]) in the Wakeup Configuration Regis- ter (WKCFG).

  • Page 118: Table 5-29. Banks 0 And 1 - Common Control And Status Registers

    It indicates which wakeup event and/or PME occurred. (See Section or software reset. Detected wakeup events that are enabled issue a power-up request the or software reset. It enables access to CEIR registers. AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module Reset Value: 00h...

  • Page 119: Table 5-30. Bank 1 - Ceir Wakeup Configuration And Control Registers

    Bank 1, Offset 09h This register is set to 14h on power-up of V Reserved. CEIR Pulse Change, Range 0, High Limit. AMD Geode™ SC1200/SC1201 Processor Data Book CEIR Wakeup Control Register - IRWCR (R/W) or software reset. Reserved CEIR Wakeup Address Register - IRWAD (R/W) or software reset.
  • Page 120 CEIR Wakeup Range 3 Registers IRWTR3L Register (R/W) or software reset. IRWTR3H Register (R/W) or software reset. AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module Reset Value: 07h Reset Value: 0Bh Reset Value: 50h Reset Value: 64h...

  • Page 121: Access.bus Interface

    (8 bits), an Acknowledge signal must follow. The following sections provide further details of this process. AMD Geode™ SC1200/SC1201 Processor Data Book 32579B During each clock cycle, the slave can stall the master while it handles the previous data or prepares new data.

  • Page 122: Figure 5-15. Access.bus Data Transaction

    Clock Line Held Byte Complete Low by Receiver Interrupt Within Receiver While Interrupt is Serviced 2 3 - 6 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module Stop Condition Transmitter Stays Off Bus During Acknowledge Clock Acknowledge Signal From Receiver...

  • Page 123: Master Mode

    1 - 7 Start Address R/W ACK Condition Figure 5-17. A Complete ACCESS.bus Data Transaction AMD Geode™ SC1200/SC1201 Processor Data Book 5.7.6 Arbitration on the Bus Multiple master devices on the bus require arbitration between their conflicting bus access demands. Control of the bus is initially determined according to address bits and clock cycle.
  • Page 124 Follow the address send sequence, as described pre- viously in "Sending the Address Byte". If the ACB was awaiting handling due to ACBST[3] = 1, clear it only after writing the requested address and direction to ACBSDA. AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module...
  • Page 125 ACBCST[2] and ACBST[2] are set. If ACBST[0] = 1 (i.e., slave transmit mode) ACBST[6] is set to indicate that the buffer is empty. AMD Geode™ SC1200/SC1201 Processor Data Book 32579B If ACBCTL1[2] is set, an interrupt is generated if both ACBCTL1[2] and ACBCTL16 are set.

  • Page 126: Table 5-31. Acb Register Map

    ACBADDR. ACB Own Address ACBCTL2. ACB Control 2 Table 5-32. ACB Registers ACB Serial Data Register - ACBSDA (R/W) ACB Status Register - ACBST (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module Reset Value Reset Value: xxh Reset Value: 00h...
  • Page 127 GCMEN (Global Call Match Enable). 0: Global call match disabled. 1: Global call match enabled. AMD Geode™ SC1200/SC1201 Processor Data Book Table 5-32. ACB Registers (Continued) ACB Control Status Register - ACBCST (R/W) ACB Control Register 1 - ACBCTL1 (R/W)
  • Page 128 0: ACB is disabled, ACBCTL1, ACBST and ACBCST registers are cleared, and clocks are halted. 1: ACB is enabled. Table 5-32. ACB Registers (Continued) ACB Own Address Register - ACBADDR (R/W) ACB Control Register 2 - ACBCTL2 (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module Reset Value: xxh Reset Value: 00h...

  • Page 129: Legacy Functional Blocks

    405h Table 5-34. Parallel Port Register Map for Second Level Offset Second Level Offset Type AMD Geode™ SC1200/SC1201 Processor Data Book 5.8.1 Parallel Port The Parallel Port supports all IEEE1284 standard commu- nication modes: Compatibility (known also as Standard or...

  • Page 130: Table 5-35. Parallel Port Bit Map For First Level Offset

    Channel RSVD Revision Address 1.7 or 1.9 Enable Select PP DMA Request Inactive Time Demand ECP IRQ Channel Number Enable AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module ERR# RSVD Status Timeout Status Printer Ini- Automatic Data tialization Line Feed...

  • Page 131: Figure 5-18. Uart Mode Register Bank Architecture

    Banks 0 through 3. Offset Type When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 5-38 on page 132. AMD Geode™ SC1200/SC1201 Processor Data Book Bank 1 Bank 0 Offset 07h...

  • Page 132: Table 5-38. Bank Selection Encoding

    RXFLV. RX_FIFO Level TXFLV. TX_FIFO Level Table 5-41. Bank 3 Register Map Name MRID. Module and Revision ID SH_LCR. Shadow of LCR SH_FCR. Shadow of FIFO Control BSR. Bank Select RSVD. Reserved AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module Bank Selected...

  • Page 133: Table 5-42. Bank 0 Bit Map

    04h-07h RSVD When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 5-38 on page 132. AMD Geode™ SC1200/SC1201 Processor Data Book Table 5-42. Bank 0 Bit Map Bits...

  • Page 134: Table 5-44. Bank 2 Bit Map

    BSR[6:0] (Bank Select) RSVD PRESL[1:0] Reserved RSVD RSVD Table 5-45. Bank 3 Bit Map Bits MID[3:0] SBRK STKP TXFHT[1:0] RSVD BSR[6:0] (Bank Select) RSVD AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module RSVD EXT_SL RSVD RFL[4:0] TFL[4:0] RID[3:0] WLS[1:0] TXSR RXSR FIFO_EN...

  • Page 135: Figure 5-19. Ircp/Sp3 Register Bank Architecture

    Banks 0 through 7. Offset Type When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 5-47. AMD Geode™ SC1200/SC1201 Processor Data Book Bank 0 Offset 07h Offset 06h...

  • Page 136: Table 5-47. Bank Selection Encoding

    BGD(H). Baud Generator Divisor Port (High Byte) EXCR1. Extended Control 1 BSR. Bank Select EXCR2. Extended Control 2 RSVD. Reserved TXFLV. TX FIFO Level RXFLV. RX FIFO Level AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module Bank Selected Functionality UART + IR IR Only...

  • Page 137: Table 5-50. Bank 3 Register Map

    SuperI/O Module Offset Type 04h-07h Offset Type Offset Type AMD Geode™ SC1200/SC1201 Processor Data Book Table 5-50. Bank 3 Register Map Name MID. Module and Revision Identification SH_LCR. Link Control Shadow SH_FCR. FIFO Control Shadow BSR. Bank Select RSVD. Reserved Table 5-51.

  • Page 138: Table 5-53. Bank 6 Register Map

    BSR[6:0] (Bank Select) RSVD LOOP IR_PLS TXEMP TXRDY BRK/ MAX_LEN PHY_ERR Scratch Data TXUR RXACT/ RXWDG/ RXBSY LOST_FR AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module MS_IE LS_IE TXLDL_IE RXHDL_IE MS_IE LS_IE TXLDL_IE RXHDL_IE RXFT IPR[1:0] MS_EV LS_EV/ TXLDL_EV RXHDL_EV...

  • Page 139: Table 5-56. Bank 1 Bit Map

    Offset Name TMR(L) TMR(H) IRCR1 BKSE TFRL(L)/ TFRCC(L) TFRL(H)/ TFRCC(H) AMD Geode™ SC1200/SC1201 Processor Data Book Table 5-56. Bank 1 Bit Map Bits LBGD[7:0] (Low Byte Data) LBGD[15:8] (High Byte Data) RSVD SBRK STKP BSR[6:0] (Bank Select) RSVD Table 5-57. Bank 2 Bit Map...

  • Page 140: Table 5-60. Bank 5 Bit Map

    MBF[3:0] RSVD Table 5-62. Bank 7 Bit Map Bits T_OV RXHSC RCDM_DS BSR[6:0] (Bank Select) SIRC[2:0] RSVD IRSL0_DS RXINV IRSL21_DS AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module TX_MS MDRS IRMSSL IR_FDPLX BAD_CRC OVR1 RSVD TXCRC_INV TXCRC_DS MPW[3:0] SPW[3:0] FPL[3:0]...

  • Page 141: 6.0Core Logic Module

    • PCI master for AC97 and IDE controllers • Subtractive agent for unclaimed transactions • Supports PCI initiator-to-Sub-ISA cycle translations • PCI-to-Sub-ISA interrupt mapper/translator AMD Geode™ SC1200/SC1201 Processor Data Book 32579B 6.0Core Logic Module • External PCI bus — Devices internal to the Core Logic module (IDE, Audio, USB, Sub-ISA, etc.) cannot master to memory...

  • Page 142: Module Architecture

    • ACPI compliant power management (includes GPIO interfaces, such as joystick) • Integrated audio controller • Low Pin Count (LPC) Interface Fast-PCI 33-66 MHz PCI Interface 33 MHz Config. Reg. X-Bus Legacy ISA/PIC/PIT/DMA Sub-ISA AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module AC97 Audio Controller...
  • Page 143 The Core Logic module decodes the serial packet after each transmission and performs the power management tasks related to video retrace. For more information on the Serial Packet register refer to the AMD Geode™ GX1 Processor Data Book.

  • Page 144: Ide Controller

    PIO mode which that device reports it supports. The PIO command cycle timing for a particular device must be the timing value for the lowest PIO mode for both devices on the channel. AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module...

  • Page 145: Table 6-1. Physical Region Descriptor Format

    31 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Memory Region Physical Base Address [31:1] (IDE Data Buffer) Reserved AMD Geode™ SC1200/SC1201 Processor Data Book Physical Region Descriptor Format Each physical memory region to be transferred is described by a Physical Region Descriptor (PRD) as illus- trated in Table 6-1.

  • Page 146: Table 6-2. Ultradma/33 Signal Definitions

    Also listed in the bit formats are recommended values for both Multiword DMA Modes 0-2 and UltraDMA/33 Modes 0-2. Note that these are only recommended settings and are not 100% tested. AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module...

  • Page 147: Universal Serial Bus

    — DOCR# is asserted on memory read transactions from DOCCS# window (i.e., when both DOCCS# and MEMR# are active, DOCR# is active; otherwise, it is inactive). AMD Geode™ SC1200/SC1201 Processor Data Book 32579B • DOCW — DOCW# is asserted on memory write transactions to DOCCS# window (i.e., when both DOCCS# and...

  • Page 148: Figure 6-2. Non-Posted Fast-Pci To Isa Access

    PCI cycles from occupying too much band- width and allows access to other PCI traffic. Figure 6-3 on page 149 shows the relationship of PCI cycles to an ISA cycle with PCI delayed transactions enabled. AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module...

  • Page 149: Figure 6-3. Pci To Isa Cycles With Delayed Transaction Enabled

    PCI data bus. When the DMA requestor is the bus owner, the Core Logic module allows 8/16-bit data transfer between the Sub-ISA bus and the PCI data bus. AMD Geode™ SC1200/SC1201 Processor Data Book 32579B 6.2.5.4 I/O Recovery Delays...

  • Page 150: Figure 6-4. Isa Dma Read From Pci Memory

    PCI cycle, asserts FRAME#, and negates an internal IOCHRDY. This assures the DMA cycle does not complete before the PCI cycle has provided or accepted the data. IOCHRDY is internally asserted when IRDY# and TRDY# are sampled active. AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module...

  • Page 151: Table 6-3. Cycle Multiplexed Pci / Sub-Isa Balls

    74HCT245 or 74FCT245 type transceivers. The RD# (an AND of IOR#, MEMR#) signal can be used as DIR control while TRDE# is used as enable control. AMD Geode™ SC1200/SC1201 Processor Data Book Table 6-3. Cycle Multiplexed PCI / Sub-ISA Balls AD10...

  • Page 152: Figure 6-6. Pci Change To Sub-Isa And Back

    Each channel can transfer data in 128 KB pages. Channels 5, 6, and 7 transfer 16-bit WORDs on even byte boundaries only. Channels 5 through 7 are not supported. AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module...
  • Page 153 For read transfer types, the Core Logic module reads data from memory and write it to the I/O device associated with the DMA channel. AMD Geode™ SC1200/SC1201 Processor Data Book 32579B For write transfer types, the Core Logic module reads data from the I/O device associated with the DMA channel and write to the memory.

  • Page 154: Figure 6-7. Pit Timer

    PIT state by reading the PIT’s counter and write only registers. The read sequence for the shadow register is listed in F0 Index BAh (see Table 6-29 on page 190). AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module IRQ0 F0 Index 50h[4]...

  • Page 155: Figure 6-8. Pic Interrupt Controllers

    IRQ14 (muxed with TFTD1), and IRQ9 (muxed with IDE_DATA6) More of the IRQs are available through the use of SERIRQ (muxed with GPIO39) function. See Table 6-4. AMD Geode™ SC1200/SC1201 Processor Data Book Table 6-4. PIC Interrupt Mapping Master IRQ0...

  • Page 156: Figure 6-9. Pci And Irq Interrupt Mapping

    A20M# state and the SMI handler sets the A20M# state inside the GX1 module. This method is used for both the Port 092h (PS/2) and Port 061h (key- board) methods of controlling A20M#. AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module Level/Edge Sensitivity...

  • Page 157: Keyboard Support

    Bit 2 = ERR_EN (PERR#/SERR# Enable) Bit 3 = IOCHK_EN (IOCHK Enable) I/O Port 070h: RTC Index Register (WO) Bit 72 = NMI (NMI Enable) AMD Geode™ SC1200/SC1201 Processor Data Book 6.2.8 Keyboard Support The Core Logic module can actively decode the keyboard controller I/O Ports 060h, 062h, 064h and 066h, and gener- ate an LPC bus cycle.

  • Page 158: Power Management Logic

    In this state, the GX1 module is in Suspend Refresh mode (for details, see the Power Management section of the AMD Geode™ GX1 Processor Data Book, and Section 6.2.9.5 "Usage Hints" on page 161). PCI arbitration should be disabled prior entering the C3...

  • Page 159: Table 6-5. Wakeup Events Capability

    IRRX1 (Infrared) GPWIO[2:0] RI2# (UART2) Temporarily exits state. AMD Geode™ SC1200/SC1201 Processor Data Book powered up. The system designer can decide which other system devices to power off with the PWRCNT1 pin. No reset is performed, when exiting this state. The SC1200/SC1201 processor keeps all context in this state.

  • Page 160: Table 6-6. Power Planes Control Signals Vs. Sleep States

    Event Power Button Power Button Override Bus Master Request Thermal Monitoring ACPI Timer On or Off GPIO SDATA_IN2 (AC97) On or Off IRRX1 RI2# GPWIO On or Off Internal SMI signal AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module...
  • Page 161 • When SCI_EN bit is 0, ONCTL# and PWRCNT[2:1] are de-asserted immediately regardless of the PWRBTN_EN bit. AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Power Button Override When PWRBTN# is 0 for more than four seconds, ONCTL# and PWRCNT[2:1] are de-asserted (i.e., the system transi- tions to the SL5 state, “Soft Off”).
  • Page 162 Video activity is defined as any access to the VGA register space, the VGA frame buffer, the graphics accelerator control registers and the configured graphics frame buffer. AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module 6.2.10.3 "Peripheral...
  • Page 163 If F0 Index 96h[1] = 1: Disable Suspend Modulation when an SMI occurs until a read to the SMI Speedup Disable register (F1BAR0+I/O Offset 08h). AMD Geode™ SC1200/SC1201 Processor Data Book 32579B The SMI Speedup Disable register prevents VSA software from entering Suspend Modulation while operating in SMM.
  • Page 164 F1BAR1+I/O Offset 1Ch) provides the ACPI counter. The counter counts at 14.31818/4 MHz (3.579545 MHz). If SMI generation is enabled (F0 Index 83h[5] = 1), an SMI or SCI is generated when bit 23 toggles. AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module...

  • Page 165: Figure 6-11. General Purpose Timer And Udef Trap Smi Tree Example

    Other_SMI Top Level Figure 6-11. General Purpose Timer and UDEF Trap SMI Tree Example AMD Geode™ SC1200/SC1201 Processor Data Book These two registers are identical except that reading the register at F1BAR0+I/O Offset 02h clears the status. Since all SMI sources report to the Top Level SMI Status register, many of its bits combine a large number of events requiring a second level of SMI status reporting.

  • Page 166: Table 6-9. Device Power Management Programming Summary

    F1BAR0+I/O Offset 04h[4] 88h[7:0], 89h[7:0], 8Bh[4] F1BAR0+I/O Offset 04h[0] 8Ah[7:0], 8Bh[5,3,2] F1BAR0+I/O Offset 04h[1] 94h[15:0], 96h[2:0] 8Dh[7:0], A8h[15:0] 8Ch[7:0] AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module Second Level SMI Status/With Clear F5h[3] F5h[2] F5h[1] F5h[7] F1BAR0+I/O Offset 02h[6]...

  • Page 167: Gpio Interface

    16-Bit output to codec. Slot in use is determined by F3BAR0+Memory Offset 08h[19]. 6 or 11 16-Bit input from codec. Slot in use is determined by F3BAR0+Memory Offset 08h[20]. AMD Geode™ SC1200/SC1201 Processor Data Book 32579B • Trap accesses for MIDI UART interface at I/O Port 300h- 301h or 330h-331h.

  • Page 168: Table 6-11. Physical Region Descriptor Format

    SMI generated by the EOP from the first PRD allows the software to refill Audio Buffer_1. The second SMI refills Audio Buffer_2. The third SMI refills Audio Buffer_1 and so on. Byte 2 Reserved AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module Byte 1 Byte 0 Size [15:1]...

  • Page 169: Figure 6-12. Prd Table Example

    EOT = 0 EOP = 0 JMP = 1 AMD Geode™ SC1200/SC1201 Processor Data Book Table Address register is incremented by 08h and is now pointing to PRD_3. The SMI Status register is read to clear the End of Page status flag. Since Audio Buffer_1 is now empty, the software can refill it.

  • Page 170: Figure 6-13. Ac97 V2.0 Codec Signal Connections

    The bit formats for these registers are given in Table 6-38 "F3BAR0+Memory Offset: Audio Configuration Registers" on page 263. BIT_CLK XTAL_I SYNC Codec1 PC_BEEP SDATA_OUT SDATA_IN BIT_CLK XTAL_I Codec2 SYNC (Optional) PC_BEEP SDATA_OUT SDATA_IN2 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module...
  • Page 171 • I/O Trap SMI and Fast Write Status Register (F3BAR0+Memory Offset 14h) • I/O Trap SMI Enable Register (F3BAR0+Memory Offset 18h) AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Audio SMI Status Reporting Registers The Top SMI Status Mirror and Status registers are the top...

  • Page 172: Figure 6-14. Audio Smi Tree Example

    SER_INTR_SMI SMI is I/O Trap Bit 0 I/O_TRAP_SMI Second Level Figure 6-14. Audio SMI Tree Example AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module Call internal SMI handler to take appropriate action F3BAR0+Memory Offset 14h Read to Clear to determine...

  • Page 173: Figure 6-15. Typical Setup

    The mother- board BIOS should be able to configure all devices at boot. AMD Geode™ SC1200/SC1201 Processor Data Book 32579B • Support desktop and mobile implementations. • Enable support of a variable number of wait states.

  • Page 174: Table 6-12. Cycle Types

    • Only 8- or 16-bit DMA, depending on channel number. Does not support the optional larger transfer sizes. • Only one external DRQ pin. AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module (Bytes) 1 or 2 1 or 2...

  • Page 175: Register Descriptions

    The device number depends upon the IDSEL Strap Override bit (F5BAR0+I/O Offset 04h[0]). This bit allows selection of the address lines to be used as the IDSEL. By Default: IDSEL = AD28 (1001 0) for F0-F5, AD29 (1001 1) for PCIUSB. AMD Geode™ SC1200/SC1201 Processor Data Book 6.3.1...

  • Page 176: Table 6-14. F0: Pci Header/Bridge Configuration Registers For Gpio And Lpc Support Summary

    (although accessed through the Core Logic PCI configuration registers). Refer to Section 7.3 "Reg- ister Descriptions" on page 333 for details. GPIO and LPC Support Summary AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Register Summary Reset Reference...
  • Page 177 Suspend Notebook Command Register B0h-B3h Reserved Floppy Port 3F2h Shadow Register Floppy Port 3F7h Shadow Register Floppy Port 1F2h Shadow Register Floppy Port 1F7h Shadow Register AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Reset Reference Value (Table 6-29) 0000FFF0h Page 200...
  • Page 178 Second Level PME/SMI Status Register 4 F8h-FFh Reserved Core Logic Module - Register Summary Reset Value (Table 6-29) 00000000h 00000000h 00000000h AMD Geode™ SC1200/SC1201 Processor Data Book Reference Page 217 Page 217 Page 217 Page 218 Page 218 Page 218 Page 218 Page 218...

  • Page 179: Table 6-15. F0Bar0: Gpio Support Registers Summary

    LAD_D0 — LPC Address Decode 0 Register 18h-1Bh LAD_D1 — LPC Address Decode 1 Register 1Ch-1Fh LPC_ERR_SMI — LPC Error SMI Register 20h-23h LPC_ERR_ADD — LPC Error Address Register AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Reset Reference Value (Table 6-30) FFFFFFFFh...

  • Page 180: Table 6-17. F1: Pci Header Registers For Smi Status And Acpi Support Summary

    Reset Value (Table 6-33) 0000h 0000h 0000h 0000h 0000h xxxxxxxxh 0000h 0000h 00000000h AMD Geode™ SC1200/SC1201 Processor Data Book Reference Page 236 Page 236 Page 236 Page 236 Page 236 Page 236 Page 236 Page 236 Page 236 Page 236...

  • Page 181: Table 6-19. F1Bar1: Acpi Support Registers Summary

    GPWIO Data Register Reserved 18h-1Bh ACPI SCI_ROUTING Register 1Ch-1Fh PM_TMR — ACPI Timer Register PM2_CNT — PM2 Control Register 21h-FFh Not Used AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Reset Reference Value (Table 6-34) 00000000h Page 247 Page 247 Page 247...

  • Page 182: Table 6-20. F2: Pci Header Registers For Ide Controller Support Summary

    00000000h 00000001h 100Bh 0502h 00009172h 00077771h 00009172h 00077771h 00009172h 00077771h 00009172h 00077771h AMD Geode™ SC1200/SC1201 Processor Data Book Reference Page 256 Page 256 Page 256 Page 256 Page 256 Page 256 Page 256 Page 256 Page 256 Page 256 Page 256...

  • Page 183: Table 6-21. F2Bar4: Ide Controller Support Registers Summary

    VSA audio interface control register block (summarized in Table 6-23). 14h-2Bh Reserved 2Ch-2Dh Subsystem Vendor ID 2Eh-2Fh Subsystem ID 30h-FFh Reserved AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Name 00000000h 00000000h 040100h 00000000h Reset Reference Value (Table 6-36)

  • Page 184: Table 6-23. F3Bar0: Audio Support Registers Summary

    0000h 0000h 00000000h 0000h 0000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h AMD Geode™ SC1200/SC1201 Processor Data Book Reference Page 263 Page 263 Page 263 Page 264 Page 264 Page 265 Page 266 Page 267 Page 268 Page 269 Page 271...

  • Page 185: Table 6-24. F5: Pci Header Registers For X-Bus Expansion Support Summary

    Width I/O Offset (Bits) Type Name 00h-03h I/O Control Register 1 04h-07h I/O Control Register 2 08h-0Bh I/O Control Register 3 AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Reset Reference Value (Table 6-39) 100Bh Page 277 0505h Page 277 0000h...

  • Page 186: Table 6-26. Pciusb: Usb Pci Configuration Register Summary

    Core Logic Module - Register Summary Reset Value (Table 6-41) 0E11h A0F8h 0280h 0C0310h 00000000h 0E11h A0F8h 000F0000h AMD Geode™ SC1200/SC1201 Processor Data Book Reference Page 283 Page 283 Page 283 Page 284 Page 284 Page 284 Page 284 Page 284 Page 284...

  • Page 187: Table 6-27. Usb_Bar: Usb Controller Registers Summary

    58h-5Bh HcRhPortStatus[2] 5Ch-5Fh HcRhPortStatus[3] 60h-9Fh Reserved 100h-103h HceControl 104h-107h HceInput 108h-10Dh HceOutput 10Ch-10Fh HceStatus AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Reference Reset Value (Table 6-42) 00000110h Page 285 00000000h Page 285 00000000h Page 286 00000000h Page 286 00000000h Page 287...

  • Page 188: Table 6-28. Isa Legacy I/O Register Summary

    Page 300 Page 300 Page 300 Page 300 Page 300 Page 301 Page 301 Page 301 Page 301 Page 301 Page 301 Page 301 Page 301 Page 301 Page 301 Page 301 Page 301 AMD Geode™ SC1200/SC1201 Processor Data Book...
  • Page 189 Secondary IDE Registers 376h-377h 1F0-1F7h/ Primary IDE Registers 3F6h-3F7h 4D0h Interrupt Edge/Level Select Register 1 4D1h Interrupt Edge/Level Select Register 2 AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Reference Page 301 Page 301 Page 301 Page 301 Page 302 Page 302...

  • Page 190: Chipset Register Space

    (described in Section 6.4.1.1 "GPIO Support Registers" on page 224 and Section 6.4.1.2 "LPC Support Registers" on page 228). Vendor Identification Register (RO) Device Identification Register (RO) PCI Command Register (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 100Bh Reset Value: 0500h Reset Value: 000Fh...
  • Page 191 This bit is always set to 1. Reserved. (Read Only) Must be set to 0 for future use. Index 08h Index 09h-0Bh AMD Geode™ SC1200/SC1201 Processor Data Book PCI Status Register (R/W) Device Revision ID Register (RO) PCI Class Code Register (RO)
  • Page 192 Base Address Register 0 - F0BAR0 (R/W) Base Address Register 1 - F0BAR1 (R/W) Reserved Subsystem Vendor ID (RO) Subsystem ID (RO) Reserved AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00h Reset Value: 00h Reset Value: 80h Reset Value: 00h Reset Value: 00000001h...
  • Page 193 1: Enable. Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9]. Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[5]. AMD Geode™ SC1200/SC1201 Processor Data Book PCI Function Control Register 1 (R/W) PCI Function Control Register 2 (R/W)
  • Page 194 Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Reserved Delayed Transactions Register (R/W) ® ® Windows ), this bit should be set to 0. Reset Control Register (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00h Reset Value: 02h Reset Value: 01h...
  • Page 195 F0BAR0 (PCI Function 0, Base Address Register 0). F0BAR0, pointer to I/O mapped GPIO configuration registers. 0: Disable. 1: Enable. Reserved. Must be set to 0. Index 48h-4Bh AMD Geode™ SC1200/SC1201 Processor Data Book Reserved PCI Functions Enable Register (R/W) Miscellaneous Enable Register (R/W) Reserved...
  • Page 196 PIT Control/ISA CLK Divider (R/W) 100: Divide by 5 101: Divide by 6 110: Divide by 7 111: Divide by 8 ISA I/O Recovery Control Register (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: FFFFFFFFh Reset Value: 7Bh Reset Value: 40h...
  • Page 197 Generate SMI on A20M# Toggle. 0: Disable. 1: Enable. This bit must be set to 1. SMI status is reported at F1BAR0+I/O Offset 00h/02h[7]. AMD Geode™ SC1200/SC1201 Processor Data Book ROM/AT Logic Control Register (R/W) Alternate CPU Support Register (R/W) 32579B Reset Value: 98h...
  • Page 198 ROM configuration is at F0 Index 52h[2:0]. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Reserved Decode Control Register 1 (R/W) Decode Control Register 2 (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00h Reset Value: 01h Reset Value: 20h...
  • Page 199 0011: IRQ3 INTC# (Ball C9) Target Interrupt. 0000: Disable 0001: IRQ1 0010: Reserved 0011: IRQ3 Index 5Eh-5Fh AMD Geode™ SC1200/SC1201 Processor Data Book PCI Interrupt Steering Register 1 (R/W) 0100: IRQ4 1000: Reserved 0101: IRQ5 1001: IRQ9 0110: IRQ6 1010: IRQ10...
  • Page 200 1111: 1 MB = FFF00000h-FFFFFFFFh All other settings for these bits are reserved. IOCS1# Base Address Register (R/W) IOCS1# Control Register (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00000000h Reset Value: 00h Reset Value: 0000FFF0h Reset Value: 0000h...
  • Page 201 31:27 Reserved. Must be set to 0. DiskOnChip Chip Select Positive Decode (DOCCS#). 0: Disable. 1: Enable. AMD Geode™ SC1200/SC1201 Processor Data Book 01111: 16 Bytes 11111: 32 Bytes All other combinations are reserved. Reserved IOCS0# Base Address Register (R/W)
  • Page 202 This bit must be set to 1 immediately after POST for power management resources to function. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Power Management Enable Register 1 (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00h...
  • Page 203 — COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is included). Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[3]. AMD Geode™ SC1200/SC1201 Processor Data Book Power Management Enable Register 2 (R/W) 32579B...
  • Page 204 If an access occurs in the address ranges selected in F0 Index 93h[5], the timer is reloaded with the programmed count. Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[0]. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 AMD Geode™ SC1200/SC1201 Processor Data Book...
  • Page 205 — COM4: I/O Port 2E8h-2EFh. Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[2]. AMD Geode™ SC1200/SC1201 Processor Data Book Power Management Enable Register 3 (R/W) 32579B Reset Value: 00h...
  • Page 206 VGA Timer. SMI status is reported at F1BAR0+I/O Offset 00h/02h[6] (top level only). Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Power Management Enable Register 4 (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00h...
  • Page 207 GPWIO0 SMI Status. Indicates whether or not an SMI was caused by a transition on the GPWIO0 pin. 0: No. 1: Yes. To enable SMI generation: 1) Ensure that GPWIO0 is enabled as an input: F1BAR1+I/O Offset 15h[0] = 0. 2) Set F1BAR1+I/O Offset 15h[4] to 1. AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Reset Value: 00h...
  • Page 208 Idle Timer Count Register (F0 Index 98h). 0: No. 1: Yes. To enable SMI generation, set F0 Index 81h[0] to 1. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00h...
  • Page 209 Primary Hard Disk Access Trap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to the primary hard disk. 0: No. 1: Yes. To enable SMI generation, set F0 Index 82h[0] to 1. AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Reset Value: 00h...
  • Page 210 164 for a discussion on the limitations of producing count error with small values. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00h Reset Value: 00h...
  • Page 211 Re-trigger General Purpose Timer 1 on Primary Hard Disk Activity. 0: Disable. 1: Enable. Any access to the primary hard disk address range selected in F0 Index 93h[5], reloads General Purpose Timer 1. AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Reset Value: 00h...
  • Page 212 A typical value here would be 50 msec to 100 msec. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 IRQ Speedup Timer Count Register (R/W) Video Speedup Timer Count Register (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00h Reset Value: 00h Reset Value: 00h...
  • Page 213 The ratio of SUSP# asserted-to-de-asserted sets up an effective (emulated) clock frequency, allowing the power manager to reduce GX1 module power consumption. This counter is prematurely reset if an enabled speedup event occurs (i.e., IRQ and video speedups). AMD Geode™ SC1200/SC1201 Processor Data Book VGA Timer Count Register (R/W) Reserved...
  • Page 214 Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Suspend Configuration Register (R/W) Reserved Floppy Disk Idle Timer Count Register (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00h Reset Value: 00h Reset Value: 0000h Reset Value: 0000h...
  • Page 215 Software clears the overflow register when new evaluations are to begin. The count contained in this regis- ter can be combined with other data to determine the type of video accesses present in the system. Index AAh-ABh AMD Geode™ SC1200/SC1201 Processor Data Book Video Idle Timer Count Register (R/W) Video Overflow Count Register (R/W)
  • Page 216 Floppy Port 3F2h Shadow Register (RO) Floppy Port 3F7h Shadow Register (RO) Floppy Port 372h Shadow Register (RO) Floppy Port 377h Shadow Register (RO) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 0000h Reset Value: 00h Reset Value: 00h Reset Value: 00h...
  • Page 217 Note: The LSB/MSB of the count is the Counter base value, not the current value. Bits [7:6] of the command words are not used. AMD Geode™ SC1200/SC1201 Processor Data Book DMA Shadow Register (RO) PIC Shadow Register (RO) PIT Shadow Register (RO)
  • Page 218 1001: 9 msec 0110: 6 msec 1010: 10 msec 0111: 7 msec 1011: 11 msec Reserved AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: xxh Reset Value: 00h 1100: 12 msec 1101: 13 msec 1110: 14 msec 1111: 15 msec...
  • Page 219 Software SMI. A write to this location generates an SMI. The data written is irrelevant. This register allows software entry into SMM via normal bus access instructions. Index D1h-EBh AMD Geode™ SC1200/SC1201 Processor Data Book User Defined Device 1 Control Register (R/W) User Defined Device 2 Control Register (R/W)
  • Page 220 Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Timer Test Register (R/W) Reserved Second Level PME/SMI Status Register 1 (RC) Second Level PME/SMI Status Register 2 (RC) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00h Reset Value: 00h Reset Value: 00h Reset Value: 00h...
  • Page 221 Hard Disk Idle Timer Count register (F0 Index ACh). 0: No. 1: Yes. To enable SMI generation, set F0 Index 83h[7] = 1. AMD Geode™ SC1200/SC1201 Processor Data Book Second Level PME/SMI Status Register 3 (RC) 32579B Reset Value: 00h...
  • Page 222 IRRX1 (CEIR) To enable SMI generation, set F1BAR1+I/O Offset 0Ch[0] = 0. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Second Level PME/SMI Status Register 4 (RC) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00h...
  • Page 223 ACPI Timer SMI Status. Indicates whether or not an SMI was caused by an ACPI Timer (F1BAR0+I/O Offset 1Ch or F1BAR1+I/O Offset 1Ch) MSB toggle. 0: No. 1: Yes. To enable SMI generation, set F0 Index 83h[5] = 1. Index F8h-FFh AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Reserved Reset Value: 00h...

  • Page 224: Table 6-30. F0Bar0+I/O Offset: Gpio Configuration Registers

    I/O mapped registers accessed through F0BAR0. GPDO0 — GPIO Data Out 0 Register (R/W) GPDI0 — GPIO Data In 0 Register (RO) GPST0 — GPIO Status 0 Register (R/W1C) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: FFFFFFFFh Reset Value: FFFFFFFFh Reset Value: 00000000h...
  • Page 225 GPIO Signal Configuration Select Register (R/W) 31:6 Reserved. Must be set to 0. AMD Geode™ SC1200/SC1201 Processor Data Book GPDO1 — GPIO Data Out 1 Register (R/W) GPDI1 — GPIO Data In 1 Register (RO) GPST1 — GPIO Status 1 Register (R/W1C)
  • Page 226 110110 = GPIO54 110111 = GPIO55 111000 = GPIO56 111001 = GPIO57 111010 = GPIO58 111011 = GPIO59 111100 = GPIO60 111101 = GPIO61 111110 = GPIO62 111111 = GPIO63 (Note) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00000044h...
  • Page 227 1: Enable. Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled (normal operation requires this bit to be 0). AMD Geode™ SC1200/SC1201 Processor Data Book GPIO Reset Control Register (R/W) 32579B Reset Value: 00000000h...

  • Page 228: Table 6-31. F0Bar1+I/O Offset: Lpc Interface Configuration Registers

    LPC bus specification 1.0, with the following exceptions: • Only 8- or 16-bit DMA, depending on channel number. Does not support the optional larger transfer sizes. • Only one external DRQ pin. AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00000000h...
  • Page 229 Reserved. Must be set to 0. IRQ15 Polarity. If LPC is selected as the interface source for IRQ15 (F0BAR1+I/O Offset 00h[15] = 1), this bit allows signal polarity selection. 0: Active high. 1: Active low. AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Reset Value: 00000000h...
  • Page 230 IRQ3 Polarity. If LPC is selected as the interface source for IRQ3 (F0BAR1+I/O Offset 00h[3] = 1), this bit allows signal polarity selection. 0: Active high. 1: Active low. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 AMD Geode™ SC1200/SC1201 Processor Data Book...
  • Page 231 1: Disable. DRQ3 Source. Selects the interface source of the DRQ3 signal. 0: ISA - DRQ3 (unavailable externally). 1: LPC - LDRQ# (ball L28). AMD Geode™ SC1200/SC1201 Processor Data Book 0100: 21 frames 1000: 25 frames 0101: 22 frames 1001: 26 frames...
  • Page 232 LPC Serial Port 1 Addressing. Serial Port 1 addresses. See bit 16 for decode. Address selection made via F0BAR1+I/O Offset 14h[7:5]. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00000000h...
  • Page 233 10: 3BCh-3BFh (+7BCh-7BFh for ECP) Selected address range is enabled via F0BAR1+I/O Offset 10h[0]. Note: 279h is read only, writes are forwarded to ISA for PnP. AMD Geode™ SC1200/SC1201 Processor Data Book 0100: 204h 1000: 208h 0101: 205h 1001: 209h...
  • Page 234 LPC Multiple Errors Status. Indicates whether or not multiple errors have occurred on LPC. 0: No. 1: Yes. Write 1 to clear. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00000000h Reset Value: 00000080h...
  • Page 235 LPC Error Memory Status. Indicates whether or not an error was generated during a memory operation on LPC. 0: No. 1: Yes. Write 1 to clear. Offset 20h-23h LPC_ERR_ADD — LPC Error Address Register (RO) 31:0 LPC Error Address. AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Reset Value: 00000000h...

  • Page 236: Table 6-32. F1: Pci Header Registers For Smi Status And Acpi Support

    Reserved Subsystem Vendor ID (RO) Subsystem ID (RO) Reserved Base Address Register 1 - F1BAR1 (R/W) Reserved AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 100Bh Reset Value: 0501h Reset Value: 0000h Reset Value: 0280h Reset Value: 00h Reset Value: 068000h...

  • Page 237: Table 6-33. F1Bar0+I/O Offset: Smi Status Registers

    This method of controlling the internal A20M# in the GX1 module is used instead of a pin. To enable SMI generation, set F0 Index 53h[0] to 1. AMD Geode™ SC1200/SC1201 Processor Data Book 32579B The registers at F1BAR0+I/O Offset 50h-FFh can also be accessed F0 Index 50h-FFh.
  • Page 238 SMI Source is Warm Reset Command. (Read to Clear) Indicates whether or not an SMI was caused by Warm Reset command 0: No. 1: Yes. Core Logic Module - SMI Status and ACPI Registers - Function 1 Top Level PME/SMI Status Register (RO/RC) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 0000h...
  • Page 239 SMI Source is ACPI. (Read Only, Read Does Not Clear) Indicates whether or not an SMI was caused by an access (read or write) to one of the ACPI registers (F1BAR1). 0: No. 1: Yes. The next level (second level) of SMI status is at F1BAR0+I/O Offset 20h. AMD Geode™ SC1200/SC1201 Processor Data Book 32579B...
  • Page 240 To enable SMI generation, set F0 Index 83h[1] = 1. Core Logic Module - SMI Status and ACPI Registers - Function 1 Second Level General Traps & Timers PME/SMI Status Mirror Register (RO) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 0000h...
  • Page 241 SMI Source is Expired General Purpose Timer 1. Indicates whether or not an SMI was caused by the expiration of Gen- eral Purpose Timer 1 (F0 Index 88h). 0: No. 1: Yes. To enable SMI generation, set F0 Index 83h[0] = 1. AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Reset Value: 0000h...
  • Page 242 Core Logic Module - SMI Status and ACPI Registers - Function 1 Reserved ACPI Timer Register (RO) Second Level ACPI PME/SMI Status Mirror Register (RO) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 0000h Reset Value: 00h Reset Value: xxxxxxxxh Reset Value: 0000h...
  • Page 243 EXT_SMI6 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI6 0: No. 1: Yes. To enable SMI generation, set bit 6 to 1. AMD Geode™ SC1200/SC1201 Processor Data Book External SMI Register (R/W) 32579B Reset Value: 0000h...
  • Page 244 EXT_SMI3 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI3. 0: No. 1: Yes. To enable SMI generation, set bit 3 to 1. Core Logic Module - SMI Status and ACPI Registers - Function 1 AMD Geode™ SC1200/SC1201 Processor Data Book...
  • Page 245 EXT_SMI1 SMI Enable. When this bit is asserted, allow EXT_SMI1 to generate an SMI on negative-edge events. 0: Disable. 1: Enable. Top level SMI status is reported at F1BAR0+00h/02h[10]. Second level SMI status is reported at bits 17 (RC) and 9 (RO). AMD Geode™ SC1200/SC1201 Processor Data Book 32579B...
  • Page 246 50h-FFh figuration Registers for GPIO and LPC Support" on page 190 for more information about these registers. Core Logic Module - SMI Status and ACPI Registers - Function 1 Not Used AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00h...

  • Page 247: Table 6-34. F1Bar1+I/O Offset: Acpi Support Registers

    1: Disable. (No debounce) GPWIO2 pin does not have debounce capability. Reserved. Must be set to 0. AMD Geode™ SC1200/SC1201 Processor Data Book are located. Table 6-34 shows the I/O mapped ACPI Sup- port registers accessed through F1BAR1. P_CNT — Processor Control Register (R/W)
  • Page 248 For the PME to generate an SCI, set F1BAR1+I/O Offset 0Ah[5] to 1 and F1BAR1+I/O Offset 0Ch[0] to 1. (See Note 2 in the general description of this register.) Write 1 to clear. Core Logic Module - SMI Status and ACPI Registers - Function 1 AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 0000h...
  • Page 249 ACPI Timer (F1BAR0+I/O Offset 1Ch or F1BAR1+I/O Offset 1Ch). Disable. Enable Offset 0Ch-0Dh 15:14 Reserved. Must be set to 0. AMD Geode™ SC1200/SC1201 Processor Data Book PM1A_CNT — PM1A Control Register (R/W) 32579B Reset Value: 0000h Reset Value: 0000h...
  • Page 250 Core Logic Module - SMI Status and ACPI Registers - Function 1 100: Sleep State SL4 101: Sleep State SL5 (Soft off) 110: Reserved 111: Reserved ACPI_BIOS_STS Register (R/W) ACPI_BIOS_EN Register (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00h Reset Value: 00h...
  • Page 251 For the PME to generate an SCI, set F1BAR1+I/O Offset 12h[6] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note 2 in the general description of this register above.) AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Reset Value: xxxxh...
  • Page 252 See F1BAR1+I/O Offset 07h[3] for debounce information. The setting of this bit can be overridden via F1BAR1+I/O Offset 15h[4] to force an SMI. Core Logic Module - SMI Status and ACPI Registers - Function 1 AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 0000h...
  • Page 253 Bit 2 of this register must be set to 0 (input) for GPWIO2 to be able to generate an SMI. If asserted, this bit overrides the setting of F1BAR1+I/O Offset 12h[10] and its status is reported in F1BAR0+I/O Offset 00h/ 02h[0]. AMD Geode™ SC1200/SC1201 Processor Data Book GPWIO Control Register 1 (R/W) GPWIO Control Register 2 (R/W)
  • Page 254 1: High. See F1BAR1+I/O Offset 07h[3] for debounce information. Offset 17h Core Logic Module - SMI Status and ACPI Registers - Function 1 GPWIO Data Register (R/W) Reserved AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00h Reset Value: 00h...
  • Page 255 Arbiter Disable. Disables the PCI arbiter when set by the OS. Used during C3 transition. 0: Arbiter not disabled. (Default) 1: Disable arbiter. Offset 21h-FFh The read value for these registers is undefined. AMD Geode™ SC1200/SC1201 Processor Data Book ACPI SCI_ROUTING Register (R/W) 0100: IRQ4 1000: IRQ8# 0101: IRQ5...

  • Page 256: Table 6-35. F2: Pci Header/Channels 0 And 1 Registers For Ide Controller Configuration

    Base Address Register 3 - F2BAR3 (RO) Base Address Register 4 - F2BAR4 (R/W) Reserved Subsystem Vendor ID (RO) Subsystem ID (RO) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 100Bh Reset Value: 0502h Reset Value: 0000h Reset Value: 0280h...
  • Page 257 Data cycle IDE_IOW# data setup (value + 1 cycle). t2WD. Data cycle IDE_IOW# pulse width minus t3 (value + 1 cycle). t1D. Data cycle address Setup Time (value + 1 cycle). AMD Geode™ SC1200/SC1201 Processor Data Book Reserved Channel 0 Drive 0 PIO Register (R/W)
  • Page 258 Ready to pause time (value + 1 cycle). Note: tRFS + 1 tRP on next clock. tACK. IDE_CS[1:0]# setup to IDE_DACK0#/DACK1# (value + 1 cycle). Core Logic Module - IDE Controller Registers - Function 2 Channel 0 Drive 0 DMA Control Register (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00077771h...
  • Page 259 The PIO Mode format is selected in F2 Index 44h[31], bit 31 of this register is defined as reserved. Index 60h-FFh AMD Geode™ SC1200/SC1201 Processor Data Book Channel 0 Drive 1 PIO Register (R/W) Channel 0 Drive 1 DMA Control Register (R/W)

  • Page 260: Table 6-36. F2Bar4+I/O Offset: Ide Controller Configuration Registers

    Core Logic Module - IDE Controller Registers - Function 2 mats of the I/O mapped IDE Controller Configuration registers that are accessed through F2BAR4. Not Used Not Used AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00h Reset Value: 00h Reset Value: 00000000h...
  • Page 261 = 1), it loads the pointer and updates this field (by adding 08h) so that is points to the next PRD. When read, this register points to the next PRD. Reserved. Must be set to 0. AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Not Used...

  • Page 262: Table 6-37. F3: Pci Header Registers For Audio Configuration

    PCI BIST Register (RO) Base Address Register - F3BAR0 (R/W) Reserved Subsystem Vendor ID (RO) Subsystem ID (RO) Reserved AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 100Bh Reset Value: 0503h Reset Value: 0000h Reset Value: 0280h Reset Value: 00h...

  • Page 263: Table 6-38. F3Bar0+Memory Offset: Audio Configuration Registers

    AC97 frame). 0: Not new. 1: New, updated in current frame. AMD Geode™ SC1200/SC1201 Processor Data Book memory mapped audio configuration registers that are accessed through F3BAR0.
  • Page 264 An SMI is then generated when the End of Page bit is set in the Audio Bus Master 3 SMI Status Register (F3BAR0+Memory Offset 39h[0] = 1). Codec Command Register (R/W) Second Level Audio SMI Status Register (RC) AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Audio Registers - Function 3 Reset Value: 00000000h Reset Value: 0000h...
  • Page 265 End of Page bit is set in the SMI Status Register (F3BAR0+Memory Offset 39h[0] = 1). The End of Page bit must be cleared before this bit can be cleared. AMD Geode™ SC1200/SC1201 Processor Data Book 32579B...
  • Page 266 Second level SMI status is reported at F3BAR0+Memory Offset 10h/12h[0]. Top level is reported at F1BAR0+I/O Offset 00h/02h[1]. SMI generation enabling is at F3BAR0+Memory Offset 18h[2]. Core Logic Module - Audio Registers - Function 3 Reset Value: 00000000h AMD Geode™ SC1200/SC1201 Processor Data Book...
  • Page 267 Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[1]. Second level SMI status is reported at F3BAR0+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR0+Memory Offset 14h[11]. AMD Geode™ SC1200/SC1201 Processor Data Book I/O Trap SMI Enable Register (R/W 32579B...
  • Page 268 0: External. 1: Internal. Reserved. Must be set to 0. Core Logic Module - Audio Registers - Function 3 10: I/O Port 260h-26Fh 11: I/O Port 280h-28Fh Internal IRQ Enable Register (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 0000h...
  • Page 269 Mask Internal IRQ7. (Write Only) 0: Disable. 1: Enable. Reserved. (Write Only) Must be set to 0. Mask Internal IRQ5. (Write Only) 0: Disable. 1: Enable. AMD Geode™ SC1200/SC1201 Processor Data Book Internal IRQ Control Register (R/W) 32579B Reset Value: 00000000h...
  • Page 270 0: Disable. 1: Enable. Assert Masked Internal IRQ4. 0: Disable. 1: Enable. Assert Masked Internal IRQ3. 0: Disable. 1: Enable. Reserved. Must be set to 0. Core Logic Module - Audio Registers - Function 3 AMD Geode™ SC1200/SC1201 Processor Data Book...
  • Page 271 The Physical Region Descriptor (PRD) table consists of one or more entries - each describing a memory region to or from which data is to be transferred. Each entry consists of two DWORDs. DWORD 0: DWORD 1: AMD Geode™ SC1200/SC1201 Processor Data Book Audio Bus Master 0 Command Register (R/W) Audio Bus Master 0 SMI Status Register (RC) Not Used...
  • Page 272 = Loop Flag (JMP) [28:16] = Reserved (0) [15:0] = Byte Count of the Region (Size) AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Audio Registers - Function 3 Reset Value: 00h Reset Value: 00h Reset Value: 00000000h...
  • Page 273 The Physical Region Descriptor (PRD) table consists of one or more entries - each describing a memory region to or from which data is to be transferred. Each entry consists of two DWORDs. DWORD 0: DWORD 1: AMD Geode™ SC1200/SC1201 Processor Data Book Audio Bus Master 2 Command Register (R/W) Audio Bus Master 2 SMI Status Register (RC) Not Used...
  • Page 274 = Loop Flag (JMP) [28:16] = Reserved (0) [15:0] = Byte Count of the Region (Size) AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Audio Registers - Function 3 Reset Value: 00h Reset Value: 00h Reset Value: 00000000h...
  • Page 275 The Physical Region Descriptor (PRD) table consists of one or more entries - each describing a memory region to or from which data is to be transferred. Each entry consists of two DWORDs. DWORD 0: DWORD 1: AMD Geode™ SC1200/SC1201 Processor Data Book Audio Bus Master 4 Command Register (R/W) Audio Bus Master 4 SMI Status Register (RC) Not Used...
  • Page 276 = Loop Flag (JMP) [28:16] = Reserved (0) [15:0] = Byte Count of the Region (Size) AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Audio Registers - Function 3 Reset Value: 00h Reset Value: 00h Reset Value: 00000000h...

  • Page 277: Table 6-39. F5: Pci Header Registers For X-Bus Expansion

    Reserved. Reserved for possible future use by the Core Logic module. Configuration of this register is programmed through the F5BAR1 Mask Register (F5 Index 48h) AMD Geode™ SC1200/SC1201 Processor Data Book Located in the PCI Header Registers of F5 are six Base...
  • Page 278 Base Address Register 5 - F5BAR5 (R/W) Reserved Subsystem Vendor ID (RO) Subsystem ID (RO) Reserved F5BAR0 Mask Address Register (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00h Reset Value: 100Bh...
  • Page 279 Index 60h-63h Scratchpad: Usually used for Device Number (R/W) BIOS writes a value, of the Device number. Expected value: 00001200h or 00001201h. AMD Geode™ SC1200/SC1201 Processor Data Book F5BAR1 Mask Address Register (R/W) F5BAR2 Mask Address Register (R/W) F5BAR3 Mask Address Register (R/W)
  • Page 280 Table 6-39. F5: PCI Header Registers for X-Bus Expansion (Continued) Description Index 64h-67h Scratchpad: Usually used for Configuration Block Address (R/W) Reset Value: 00000000h BIOS writes a value, of the Configuration Block Address. Index 68h-FFh Reserved AMD Geode™ SC1200/SC1201 Processor Data Book...

  • Page 281: Table 6-40. F5Bar0+I/O Offset: X-Bus Expansion Registers

    0: IDSEL: AD28 for Chipset Register Space (F0-F5), AD29 for USB Register Space (PCIUSB). 1: IDSEL: AD26 for Chipset Register Space (F0-F5), AD27 for USB Register Space (PCIUSB). AMD Geode™ SC1200/SC1201 Processor Data Book trol support registers. Table 6-40 shows the support regis- ters accessed through F5BAR0.
  • Page 282 IO_TEST_PORT_REG (Debug Port Pointer). These bits are used to point to the 16-bit slice of the test port bus. Core Logic Module - X-Bus Expansion Interface - Function 5 I/O Control Register 3 (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00009000h...

  • Page 283: Table 6-41. Pciusb: Usb Pci Configuration Registers

    I/O Space. Allow the USB to respond as a target to I/O cycles from the PCI bus. 0 Disable. 1: Enable. AMD Geode™ SC1200/SC1201 Processor Data Book USB Host Controller's operational register set into a 4K memory space. Once the BAR register has been initialized, and the PCI Command register at Index 04h has been set to enable the Memory space decoder, these “USB Control-...
  • Page 284 Cache Line Size Register (R/W) Latency Timer Register (R/W) Header Type Register (RO) BIST Register (RO) Base Address Register- USB_BAR0 (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 0280h Reset Value: 08h Reset Value: 0C0310h Reset Value: 00h Reset Value: 00h...

  • Page 285: Table 6-42. Usb_Bar+Memory Offset: Usb Controller Registers

    The bit is hard-coded to 0. InterruptRouting. This bit is used for interrupt routing: 0: Interrupts routed to normal interrupt mechanism (INT). 1: Interrupts routed to SMI. AMD Geode™ SC1200/SC1201 Processor Data Book Reserved Subsystem Vendor ID (RO) Subsystem ID (RO)
  • Page 286 Note: All bits are set by hardware and cleared by software. Core Logic Module - USB Controller Registers - PCIUSB HcCommandStatus Register (R/W) HcInterruptStatus Register (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value = 00000000h Reset Value = 00000000h...
  • Page 287 UnrecoverableErrorEnable. This event is not implemented. All writes to this bit will be ignored. ResumeDetectedEnable. 0: Ignore. 1: Disable interrupt generation due to Resume Detected. AMD Geode™ SC1200/SC1201 Processor Data Book HcInterruptEnable Register (R/W) HcInterruptDisable Register (R/W) 32579B Reset Value = 00000000h...
  • Page 288 HcControlCurrentED Register (R/W) HcBulkHeadED Register (R/W) HcBulkCurrentED Register (R/W) HcDoneHead Register (R/W) HcFmInterval Register (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value = 00000000h Reset Value = 00000000h Reset Value = 00000000h Reset Value = 00000000h Reset Value = 00000000h...
  • Page 289 This register is only reset by a power-on reset (PCIRST#). It is written during system initialization to configure the Root Hub. These bit should not be written during normal operation. AMD Geode™ SC1200/SC1201 Processor Data Book HcFrameRemaining Register (RO) HcFmNumber Register (RO)
  • Page 290 Write: ClearGlobalPower. Writing a 1 issues a ClearGlobalPower command to the ports. Writing a 0 has no effect. Note: This register is reset by the UsbReset state. Core Logic Module - USB Controller Registers - PCIUSB HcRhDescriptorB Register (R/W) HcRhStatus Register (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value = 00000000h Reset Value = 00000000h...
  • Page 291 Write: ClearPortSuspend. Writing a 1 initiates the selective resume sequence for the port. Writing a 0 has no effect. Read: PortSuspendStatus. 0: Port is not suspended. 1: Port is selectively suspended. Write: SetPortSuspend. Writing a 1 sets PortSuspendStatus. Writing a 0 has no effect. AMD Geode™ SC1200/SC1201 Processor Data Book HcRhPortStatus[1] Register (R/W) 32579B Reset Value = 00000000h...
  • Page 292 1: Port reset signal is active. Write: SetPortReset. Writing a 1 sets PortResetStatus. Writing a 0 has no effect. Core Logic Module - USB Controller Registers - PCIUSB HcRhPortStatus[2] Register (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value = 00000000h...
  • Page 293 Read: LowSpeedDeviceAttached. This bit defines the speed (and bud idle) of the attached device. It is only valid when CurrentConnectStatus is set. 0: Full speed device. 1: Low speed device. Write: ClearPortPower. Writing a 1 clears PortPowerStatus. Writing a 0 has no effect. AMD Geode™ SC1200/SC1201 Processor Data Book HcRhPortStatus[3] Register (R/W) 32579B Reset Value = 00000000h...
  • Page 294 Write: ClearPortEnable. Writing 1 a clears PortEnableStatus. Writing a 0 has no effect. Note: This register is reset by the UsbReset state. Offset 60h-9Fh Core Logic Module - USB Controller Registers - PCIUSB Reserved AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value = xxh...
  • Page 295 1. While this bit is 0 and CharacterPending in HceControl is set to 1, an emulation interrupt condition exists. Note: This register is the emulation side of the legacy Status register. AMD Geode™ SC1200/SC1201 Processor Data Book HceControl Register (R/W) HceInput Register (R/W) HceOutput Register (R/W)

  • Page 296: Table 6-43. Dma Channel Control Registers

    DMA Channel 2 Address Register (R/W) DMA Channel 2 Transfer Count Register (R/W) DMA Channel 3 Address Register (R/W) DMA Channel 3 Transfer Count Register (R/W) DMA Status Register, Channels 3:0 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - ISA Legacy Register Space...
  • Page 297 Reserved. Must be set to 0. Channel Mask. 0: Not masked. 1: Masked. Channel Number Mask Select. 00: Channel 0. 01: Channel 1. 10: Channel 2. 11: Channel 3. AMD Geode™ SC1200/SC1201 Processor Data Book DMA Command Register, Channels 3:0 32579B...
  • Page 298 DMA Channel 6 Address Register (R/W) DMA Channel 6 Transfer Count Register (R/W) DMA Channel 7 Address Register (R/W) DMA Channel 7 Transfer Count Register (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - ISA Legacy Register Space...
  • Page 299 Priority Mode. 0: Fixed. 1: Rotating. Timing Mode. 0: Normal. 1: Compressed. Channels 7:4. 0: Disable. 1: Enable. Reserved. Must be set to 0. AMD Geode™ SC1200/SC1201 Processor Data Book DMA Status Register, Channels 7:4 DMA Command Register, Channels 7:4 32579B...
  • Page 300 Channels 5, 6, and 7 are not supported. I/O Port 0DCh DMA Clear Mask Register Command, Channels 7:4 (W) Note: Channels 5, 6, and 7 are not supported. Core Logic Module - ISA Legacy Register Space AMD Geode™ SC1200/SC1201 Processor Data Book...
  • Page 301 Not supported. I/O Port 48Bh Note: Not supported. AMD Geode™ SC1200/SC1201 Processor Data Book Table 6-44. DMA Page Registers DMA Channel 2 Low Page Register (R/W) DMA Channel 3 Low Page Register (R/W) DMA Channel 1 Low Page Register (R/W)

  • Page 302: Table 6-45. Programmable Interval Timer Registers

    BCD Mode. 0: Binary. 1: BCD (Binary Coded Decimal). Core Logic Module - ISA Legacy Register Space PIT Timer 0 Counter PIT Timer 0 Status PIT Timer 1 Counter (Refresh) PIT Timer 1 Status (Refresh) AMD Geode™ SC1200/SC1201 Processor Data Book...
  • Page 303 11: R/W LSB, followed by MSB. Current Counter Mode. 0-5. BCD Mode. 0: Binary. 1: BCD (Binary Coded Decimal). AMD Geode™ SC1200/SC1201 Processor Data Book PIT Timer 2 Counter (Speaker) PIT Timer 2 Status (Speaker) PIT Mode Control Word Register 32579B...

  • Page 304: Table 6-46. Programmable Interrupt Controller Registers

    IRQ2 / IRQ10 Mask. 0: Not Masked. 1: Mask. Core Logic Module - ISA Legacy Register Space Master / Slave PIC ICW1 (WO) Master / Slave PIC OCW1 (except immediately after ICW1 is written) AMD Geode™ SC1200/SC1201 Processor Data Book...
  • Page 305 1: No. IRQ2 / IRQ10 Pending. 0: Yes. 1: No. AMD Geode™ SC1200/SC1201 Processor Data Book Master / Slave PIC OCW2 (WO) 100: Set rotate in Auto EOI mode 101: Rotate on non-specific EOI command 110: Set priority command (bits [2:0] must be valid)
  • Page 306 1: Yes. IRQ2 / IRQ10 In-Service. 0: No. 1: Yes. IRQ1 / IRQ9 In-Service. 0: No. 1: Yes. IRQ0 / IRQ8 In-Service. 0: No. 1: Yes. Core Logic Module - ISA Legacy Register Space AMD Geode™ SC1200/SC1201 Processor Data Book...

  • Page 307: Table 6-47. Keyboard Controller Registers

    Fast CPU Reset. WM_RST SMI is asserted to the BIOS. 0: Disable. 1: Enable. This bit must be cleared before the generation of another reset. AMD Geode™ SC1200/SC1201 Processor Data Book Port B Control Register (R/W) Port A Control Register (R/W) 32579B...

  • Page 308: Table 6-48. Real-Time Clock Registers

    Table 6-49. Miscellaneous Registers Coprocessor Error Register (W) Secondary IDE Registers (R/W) Primary IDE Registers (R/W) Interrupt Edge/Level Select Register 1 (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - ISA Legacy Register Space Reset Value: F0h Reset Value: 00h...
  • Page 309 0: Edge. 1: Level. IRQ9 Edge or Level Sensitive Select. Selects PIC IRQ9 sensitivity configuration. 0: Edge. 1: Level. Reserved. Must be set to 0. AMD Geode™ SC1200/SC1201 Processor Data Book Interrupt Edge/Level Select Register 2 (R/W) 32579B Reset Value: 00h...
  • Page 310 32579B Core Logic Module - ISA Legacy Register Space AMD Geode™ SC1200/SC1201 Processor Data Book...

  • Page 311: 7.0Video Processor Module

    • Supports chroma key and color key for both graphics and video streams • Supports alpha-blending with up to three alpha windows that can overlap one another AMD Geode™ SC1200/SC1201 Processor Data Book 7.0Video Processor Module • 8-Bit alpha values with automatic increment or decre- ment on each frame •...

  • Page 312: Module Architecture

    Vertical Upscalers, and Filters Mixer/Blender Overlay with Gamma Data RAM and Alpha Blending TVOUT Flicker Filter, Horizontal Scaling, VESA Encoder, Timing Generator, and TV Encoder AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module TFT_IF CRT_IF DACs TV_IF DACs...

  • Page 313: Functional Description

    27 MHz pixel clock, and 50 or 60 Hz refresh rate. Full frame pixel resolution and the refresh rate depends on the TV standard: NTSC, PAL, or SECAM. AMD Geode™ SC1200/SC1201 Processor Data Book 32579B If the VIP input data is full frame (conforming data) and the output is the TV interface, then the data can go directly from the VIP block to the Video Formatter.

  • Page 314: Figure 7-2. Ntsc 525 Lines, 60 Hz, Odd Field

    (Not normally User Data) Active Video Logical Line 24 — Scan Lines 287-525 Vertical Retrace - Logical Line 24 — Scan Line 264 (Not normally User Data) AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module VSYNC Start VSYNC End VSYNC Start...

  • Page 315: Figure 7-4. Vip Block Diagram

    F4BAR2 Direct Video/VBI Control Registers AMD Geode™ SC1200/SC1201 Processor Data Book data processed by the CCIR-656 decoder. For Direct Video/VBI modes, there are two FIFOs that buffer the CCIR-656 decoder’s data. A 2048-byte FIFO buffers Video data and a 128-byte FIFO buffers VBI data. The FIFOs are also used to provide clock domain changes.

  • Page 316: Table 7-1. Direct Mode And Capture Mode Configurations

    VBI at all. However, VBI data can be decoded, turned into graphic information and placed in the GX1 module’s graphics frame buffer for display. Restriction: The GX1 module’s video frame buffer cannot be used to send both video and VBI data. AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module...

  • Page 317: Figure 7-5. Capture Video Mode Bob Example Using One Video Frame Buffer

    85 frames per second Figure 7-5. Capture Video Mode Bob Example Using One Video Frame Buffer AMD Geode™ SC1200/SC1201 Processor Data Book – F4BAR2+Memory Offset 20h – Video Data Odd Base Address – F4BAR2+Memory Offset 24h – Video Data Even Base Address –...
  • Page 318 Data Even Base Address with the other buffer so that the even field will ping-pong just like the odd field. The field just received can be known by reading the Cur- rent Field bit (F4BAR2+Memory Offset 08h[24]). AMD Geode™ SC1200/SC1201 Processor Data Book normally...

  • Page 319: Figure 7-6. Capture Video Mode Weave Example Using Two Video Frame Buffers

    Internet address that is encoded on one or more of the VBI lines, or have an application decode the Closed Captioning information put in the graphics frame buffer. AMD Geode™ SC1200/SC1201 Processor Data Book Video Data Even Base F4BAR2+Memory Offset 20h Line 1 Even Field...

  • Page 320: Figure 7-7. Video Block Diagram

    Line Buffer 0 Formatter Line Buffer 1 Line Buffer 2 (3x360x32 bit) (4:2:2 or 4:2:0) 2-Tap Vertical Interpolating Upscaler 2-Tap Horizontal Interpolating Upscaler Figure 7-7. Video Block Diagram AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module 4:4:4 YUV 4:4:4/RGB 5:6:5...

  • Page 321: Figure 7-8. Horizontal Downscaler Block Diagram

    Video Input Coefficients Figure 7-8. Horizontal Downscaler Block Diagram AMD Geode™ SC1200/SC1201 Processor Data Book Maintaining Aspect Ratio The main purpose of the horizontal downscaler is to main- tain the aspect ratio of graphics data displayed on a TV, which was originally generated for CRT display.

  • Page 322: Figure 7-9. Linear Interpolation Calculation

    0 - 7 A i j , A i j , ----------- - i+1,j+1 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module Video Upscale , and A values to calculate the value of i+1,j+1 –...

  • Page 323: Figure 7-10. Mixer/Blender Block Diagram

    GRAPHICS COLOR_CHROMA_SEL Figure 7-10. Mixer/Blender Block Diagram AMD Geode™ SC1200/SC1201 Processor Data Book tion 7.2.3.1) is used on the video data when RGB mixing/ blending is desired and the RGB to YUV CSC is used on the graphics data when YUV blending is desired. If Gamma Correction (see Section 7.2.3.2) on the video data is...

  • Page 324: Table 7-2. Valid Mixing/Blending Configurations

    — Must be vertically upscaled by a factor of 2 (see • CRT/TFT and TV Display. — Can be used to support simultaneous operation. AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module Section 7.2.1.3 "Capture Video Mode", Weave subsection on page 318).
  • Page 325 (CSC_FOR_GFX = 0), the CSC is used post blending to convert the mixed/blended data from RGB to YUV for the TVOUT block. AMD Geode™ SC1200/SC1201 Processor Data Book RGB graphics data or mixed/blended graphics/video data is passed through this CSC to obtain 24-bit YUV data using the following CCIR-601-1 recommended formula: •...

  • Page 326: Figure 7-11. Graphics/Video Frame With Alpha Windows

    (see Section 5.5.3 “Hardware Cursor” in the AMD Geode™ GX1 Pro- cessor Data Book). When the software cursor is used, the cursor size and position are not defined using registers.

  • Page 327: Table 7-3. Truth Table For Alpha Blending

    ALPHAx_COLOR_REG_EN = 1 = 1) Window x ALPHAx_COLOR_REG_EN = 0 COLOR_CHROMA_SEL: F4BAR0+Memory Offset 04h[20]. GFX_INS_VIDEO: F4BAR0+Memory Offset 4Ch[8]. ALPHAx_COLOR_REG_EN: F4BAR0+Memory Offsets 68h[24], 78h[24], and 88h[24]. AMD Geode™ SC1200/SC1201 Processor Data Book Graphics Data Match Cursor Configuration Color Key GFX_INS_VIDEO = 0...

  • Page 328: Figure 7-12. Color Key And Alpha Blending Logic

    Pixel value matches normal color COLOR_CHROMA _SEL = 1 window Use graphics value for this pixel AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module COLOR_CHROMA _SEL = 1 Use video value Use graphics for this pixel value for this pixel...

  • Page 329: Figure 7-13. Tvout Block Diagram

    Graphics Y(n-1) * ½ = ½ GY(n-1) Graphics Y(n) * ½ = ½ GY(n) Graphics Y(n+1) * ½ = ½ GY(n+1) AMD Geode™ SC1200/SC1201 Processor Data Book Flicker Filter, Interlaced Video and YUV Mixing/Blending Mode This is the recommended mode. With this mode only the graphics data is flicker filtered.

  • Page 330: Figure 7-14. Dac Voltage Levels

    VREF (either internal bandgap refer- ence, or externally connected voltage reference). is the value of resistance between SETRES and (typically 470 Ω). Figure 7-14. DAC Voltage Levels AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module - full range output voltage), Monitor...

  • Page 331: Figure 7-15. Tft Power Sequence

    SC1200/SC1201 processor. FP_PWR_EN FP_VDD_ON TFTD[17:0], HSYNC, VSYNC, TFTDE, TFTDCK AMD Geode™ SC1200/SC1201 Processor Data Book TFT output signals are: • TFTD[5:0] for blue signals • TFTD[11:6] for green signals • TFTD[17:12] for red signals • HSYNC and VSYNC - sync signals •...

  • Page 332: Figure 7-16. Pll Block Diagram

    27 MHz. This PLL can be powered down via the Miscellaneous register (F4BAR0+Memory Offset 28h[12]). Phase Charge Loop Pump Filter Divider Figure 7-16. PLL Block Diagram AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module Divide...

  • Page 333: Register Descriptions

    1Ch-1Fh Palette Address Register 20h-23h Palette Data Register 24h-27h Reserved AMD Geode™ SC1200/SC1201 Processor Data Book 32579B 7.3.1 Register Summary The tables in this subsection summarize the registers of the Video Processor. Included in the tables are the regis- ter’s reset values and page references where the bit for- mats are found.
  • Page 334 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 1FFF1FFFh AMD Geode™ SC1200/SC1201 Processor Data Book Reference (Table 7-9) Page 342 Page 342 Page 343 Page 343 Page 343 Page 343 Page 343 Page 344 Page 344 Page 344...

  • Page 335: Table 7-7. F4Bar2: Vip Support Registers Summary

    2Ch-3Fh Reserved 40h-43h VBI Data Odd Base Register 44h-47h VBI Data Even Base Register 48h-4Bh VBI Data Pitch Register 4Ch-1FFh Reserved AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Reset Reference Value (Table 7-9) 00000000h Page 352 00000000h Page 352 00000000h...

  • Page 336: Table 7-8. F4: Pci Header Registers For Video Processor Support Registers

    Base Address Register 2 - F4BAR2 (R/W) Reserved Subsystem Vendor ID (RO) Subsystem ID (RO) Reserved Interrupt Line Register (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 100Bh Reset Value: 0504h Reset Value: 0000h Reset Value: 0280h Reset Value: 01h...
  • Page 337 This register selects which interrupt pin the device uses. VIP uses INTC# after reset. INTA#, INTB# or INTD# can be selected by writing 1, 2 or 4, respectively. Index 3Eh-FFh AMD Geode™ SC1200/SC1201 Processor Data Book Interrupt Pin Register (R/W) Reserved...

  • Page 338: Table 7-9. F4Bar0+Memory Offset: Video Processor Configuration Registers

    Video Configuration Register (R/W) 10: Y0 Cb Y1 Cr 11: Y0 Cr Y1 Cb 10: Y1 Y0 Y3 Y2 11: Y1 Y2 Y3 Y0 10: P1M P1L P2M P2L 11: P1M P2L P2M P1L AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00000000h...
  • Page 339 0: CRT vertical sync is normally low, and is set high during the sync interval. 1: CRT vertical sync is normally high, and is set low during the sync interval. AMD Geode™ SC1200/SC1201 Processor Data Book Display Configuration Register (R/W)
  • Page 340 H_TOTAL and H_SYNC_END are values programmed in the GX1 module’s Display Controller Timing registers (GX_BASE+Memory Offset 8330h[26:19] and 8338h[10:3], respectively). The value of (H_TOTAL – H_SYNC_END) is some- times referred to as “horizontal back porch”. For more information, see the AMD Geode™ GX1 Processor Data Book. 31:28 Reserved.
  • Page 341 VID_CLR_MASK (Video Color Mask). This mask is a 24-bit value. Zeros in the mask cause the corresponding bits in the graphics or video stream to be ignored. AMD Geode™ SC1200/SC1201 Processor Data Book Video Upscale Register (R/W) Video Color Key Register (R/W)
  • Page 342 1: Values according to the m (bits [14:8]), n (bits [3:0]), and CLK_DIV_SEL (bits [22:21]) fields. Video Processor Module - Video Processor Registers - Function 4 Reserved Miscellaneous Register (R/W) PLL2 Clock Select Register (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: xxxxxxxxh Reset Value: xxxxxxxxh Reset Value: 00001400h Reset Value: 00000000h...
  • Page 343 FLT_CO_3 (Filter Coefficient 3). For the tap-3 filter. 15:12 Reserved. 11:8 FLT_CO_2 (Filter Coefficient 2). For the tap-2 filter. Reserved. FLT_CO_1 (Filter Coefficient 1). For the tap-1 filter. AMD Geode™ SC1200/SC1201 Processor Data Book 1000: 65 1100: 108 1001: 75 1101: 135 1010: 78.5 1110: 27 1011: 94.5...
  • Page 344 Offset 48h-4Bh 31:16 Reserved. 15:8 REV_ID (Revision ID). See the AMD Geode™ SC1200/SC1201 Processor Specification Update document for value. DEV_ID (Device ID). See AMD Geode™ SC1200/SC1201 Processor Specification Update document for value. Offset 4Ch-4Fh Video De-Interlacing and Alpha Control Register (R/W) 31:22 Reserved.
  • Page 345 1: The odd frame is shifted according to the offset specified in bits [2:0]. Reserved. OFFSET (Vertical Scaler Offset). For a non-interlaced video stream and when bob de-interlacing is used, program a value of 100 (i.e., shift one line); otherwise, leave at 000. AMD Geode™ SC1200/SC1201 Processor Data Book 32579B...
  • Page 346 (GX_BASE+Memory Offset 8330h[26:19] and 8338h[10:3], respectively). The value of (H_TOTAL – H_SYNC_END) is some- times referred to as “horizontal back porch”. For more information, see the AMD Geode™ GX1 Processor Data Book. Desired screen position should not be outside a video window (F4BAR0+Memory Offset 08h and 0Ch).
  • Page 347 (GX_BASE+Memory Offset 8330h[26:19] and 8338h[10:3], respectively). The value of (H_TOTAL – H_SYNC_END) is some- times referred to as “horizontal back porch”. For more information, see the AMD Geode™ GX1 Processor Data Book. Desired screen position should not be outside a video window (F4BAR0+Memory Offset 08h and 0Ch).
  • Page 348 H_TOTAL and H_SYNC_END are values programmed in the GX1 module’s Display Controller Timing registers (GX_BASE+Memory Offset 8330h[26:19] and 8338h[10:3], respectively). The value of (H_TOTAL – H_SYNC_END) is some- times referred to as “horizontal back porch”. For more information, see the AMD Geode™ GX1 Processor Data Book. Note: Desired screen position should not be outside a video window (F4BAR0+Memory Offset 08h and 0Ch).
  • Page 349 Video FIFO Underflow (Empty). 0: No underflow has occurred. 1: Underflow has occurred. Write 1 to reset this bit. AMD Geode™ SC1200/SC1201 Processor Data Book Alpha Window 3 Color Register (R/W) Alpha Window 3 Control Register (R/W) Video Request Register (R/W)
  • Page 350 Video Processor Module - Video Processor Registers - Function 4 Reserved Video Processor Test Mode Register (R/W) VBI Line Enable Register - Odd (R/W) VBI Line Enable Register - Even (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h...
  • Page 351 GX1_VSYNC_EDGE_SEL (GX1 VSYNC Edge Select). Selects which edge of the VSYNC signal should be synchronized with the GX1 module. 0: Rising edge. 1: Falling edge. AMD Geode™ SC1200/SC1201 Processor Data Book VBI Horizontal Control Register (R/W) VBI Total Count Register - Odd (R/W) VBI Total Count Register - Even (R/W)
  • Page 352 Reserved Continuous GenLock Timeout Register (R/W) Horizontal Timing Register (R/W) Horizontal Sync Timing Register (R/W) Vertical Sync Timing Register (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00000000h Reset Value: 1FFF1FFFh Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h...
  • Page 353 EX_RES_INTRVl_16 (External Reset Interval + 16). Adds 16 frames to the external Reset Interval. These bits are relevant only if bits [27:24] (EX_RES_CTL) are set to 1000 or 1010. AMD Geode™ SC1200/SC1201 Processor Data Book Display Line End Register (R/W)
  • Page 354 1: 525 lines / 60 Hz 0: 625 lines / 50 Hz Video Processor Module - Video Processor Registers - Function 4 TVOUT Debug Register Reserved Timing & Encoder Control 1 Register AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00000440h Reset Value: 00000000h...
  • Page 355 SCPHASE (Subcarrier Phase). Defines the subcarrier phase at the start of a two-frame sequence (NTSC) or four-frame sequence (PAL). The number is: phase (in degrees) / 256. AMD Geode™ SC1200/SC1201 Processor Data Book Timing & Encoder Control 2 Register 32579B...
  • Page 356 Timing & Encoder Control 3 Register Ball No. CVBS CVBS CVBS CVBS CVBS Subcarrier Frequency Register Display Position Register Display Size Register AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00000000h Mode CVBS Super Video SCART SCART YCbCr YCbCr Reset Value: 21F07C1Fh...
  • Page 357 CC_LINE (Closed Captioning Line). This bit field selects the line on which Closed Captioning and/or Extended Data Ser- vices Data should be to encoded, programmed with the “line number minus 4”. Normally set to 17 for NTSC operation. AMD Geode™ SC1200/SC1201 Processor Data Book Closed Captioning Data Register...
  • Page 358 VBI_SCALE_OFFSET (VBI Scale Offset). This field contains a signed number between −128 and +127. This value is added to the VBI value of each pixel. Video Processor Module - Video Processor Registers - Function 4 DAC Control Register VBI Scaler Register AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00000020h Reset Value: 00000004h...

  • Page 359: Table 7-10. F4Bar2+Memory Offset: Vip Configuration Registers

    Interrupt generation can be enabled regardless of whether or not video capture (store to memory) is enabled. 0: Disable. 1: Enable. 15:11 Reserved. Must be set to 0. AMD Geode™ SC1200/SC1201 Processor Data Book are located. Table 7-10 shows the memory mapped VIP support registers accessed through F4BAR2. Video Interface Control Register (R/W) 32579B...
  • Page 360 0: VBI data is not being stored to memory. 1: VBI data is now being stored to memory. Video Processor Module - Video Processor Registers - Function 4 Video Interface Status Register (R/W) AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: xxxxxxxxh...
  • Page 361 31:0 Video Even Base Address. Base address where even video data are stored in graphics memory. Bits [3:0] are always 0, and define the required address space. AMD Geode™ SC1200/SC1201 Processor Data Book Reserved Video Current Line Register (RO) Video Line Target Register (R/W)
  • Page 362 Reserved VBI Data Odd Base Register (R/W) VBI Data Even Base Register (R/W) VBI Data Pitch Register (R/W) Reserved AMD Geode™ SC1200/SC1201 Processor Data Book Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h...

  • Page 363: 8.0Debugging And Monitoring

    EXTEST SAMPLE/PRELOAD IDCODE CLAMP Reserved Reserved BYPASS AMD Geode™ SC1200/SC1201 Processor Data Book 8.0Debugging and Monitoring 8.1.2 Optional Instruction Support The TAP supports the following IEEE optional instructions: • IDCODE Presents the contents of the Device Identification register in serial format.
  • Page 364 32579B Debugging and Monitoring AMD Geode™ SC1200/SC1201 Processor Data Book...

  • Page 365: 9.0Electrical Specifications

    Note 2. No bias. Note 3. Voltage min is -0.8V with a transient voltage of 20 ns or less. Note 4. Voltage max is 4.0V with a transient voltage of 20 ns or less. AMD Geode™ SC1200/SC1201 Processor Data Book 9.0Electrical Specifications 9.1.2...

  • Page 366: Table 9-3. Operating Conditions

    It is recommended that the voltage difference between and V leakage current. If the voltage difference exceeds 0.25V, excessive leakage current is used in gates that are connected on the boundary between voltage domains. AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications Unit Comments 3.46 3.46 3.46...

  • Page 367: Table 9-4. Power Planes Of External Interface Signals

    • Sleep (SL2): This is the lowest power state the SC1200/SC1201 processor can be in with voltage still applied to the device’s core and I/O supply pins. This is equivalent to the ACPI specification’s “S1” state. AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Balls CCCRT...

  • Page 368: Table 9-5. System Conditions Used To Measure Sc1200/Sc1201 Current During On State

    System Conditions CORE (Note 1) (Note 1) Nominal Nominal Typ Avg = 3.3V CORE = 1.8V (Nominal); CPU AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications SC1200/SC1201 processor. used. Power consumed DCLK SDRAM Frequency Frequency 50 MHz (Note 2)

  • Page 369: Table 9-7. Dc Characteristics For Active Idle, Sleep, And Off States

    I/O Pin Capacitance Output Pin Capacitance Pin Inductance Note 1. T = 25°C, f = 1 MHz. All capacitances are not 100% tested. Note 2. Not 100% tested. AMD Geode™ SC1200/SC1201 Processor Data Book = 3.3V CORE = 1.8V (Nominal); <1 <1 –...

  • Page 370: Pull-Up And Pull-Down Resistors

    KΩ to 50 KΩ. 100 KΩ resistors are within a range of 90 22.5K KΩ to 250 KΩ. Note 2. Controlled by software. 22.5K 22.5K 22.5K 22.5K AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications and for PDs assumes V Typ Value [Ω] Ball No. PU/PD (Note 1) 22.5K 22.5K 22.5K...

  • Page 371: Dc Characteristics

    Output, TRI-STATE, capable of sourcing p mA and sinking n mA WIRE Wire, no buffer Note 1. Output from these signals is open-drain and cannot be forced high. AMD Geode™ SC1200/SC1201 Processor Data Book Table 9-10. Buffer Types is 0.6V ) with weak pull-down...
  • Page 372 - not IN Unit 0.5V +0.3 (Note 1) -0.5 0.3V (Note 1) 0.7V +/-10 µA AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications Comments Comments Note 1 Comments Note 2 0 < V < V , Note 3, Note 4...
  • Page 373 Note 1. Not 100% tested. 9.2.7 DC Characteristics Symbol Parameter Input High Voltage Input Low Voltage Input Leakage Current Input Hysteresis Note 1. Not 100% tested. AMD Geode™ SC1200/SC1201 Processor Data Book Unit 0.6V +0.3 (Note 1) 0.3V µA −10 µA Unit +0.3...

  • Page 374: Figure 9-1. Differential Input Sensitivity For Common Mode Range

    (Note 1) -0.5 (Note 1) µA µA Common Mode Input Voltage (volts) Unit 0.9V 0.1V Unit AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications Comments |(D+)-(D-)| and Figure 9-1 Includes V Range Comments = -5 mA = 5 mA Comments...
  • Page 375 Signals with internal pull-ups have a maximum input leakage current of: Where V is V , or V power Signals with internal pull-downs have a maximum input leakage current of: AMD Geode™ SC1200/SC1201 Processor Data Book Unit 0.1V Unit Unit 0.9V 0.1V...

  • Page 376: Ac Characteristics

    Output Low Drive Voltage All AC tests are at V C to 85 C, C Valid Output Valid Input AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications Value (V) = 3.14V to 3.46V (3.3V nominal), = 50 pF, unless otherwise specified.

  • Page 377: Memory Controller Interface

    INPUTS Legend: A = Maximum Output Delay B = Minimum Output Delay C = Minimum Input Setup D = Minimum Input Hold Figure 9-3. Memory Controller Drive Level and Measurement Points AMD Geode™ SC1200/SC1201 Processor Data Book Valid Output 32579B...

  • Page 378: Table 9-12. Memory Controller Timing Parameters

    SHFTSDCLK field, and y is 0.45 the core clock period. Note that the SHFTSDCLK field = GX_BASE+Memory Offset 8404h[5:3]. Refer to the AMD Geode™ GX1 Proces- sor Data Book for more information.

  • Page 379: Figure 9-4. Memory Controller Output Valid Timing Diagram

    SDCLK[3:0] Control Output, MA[12:0] BA[1:0], MD[63:0] Figure 9-4. Memory Controller Output Valid Timing Diagram SDCLK_IN MD[63:0] Data Valid Read Data In Figure 9-5. Read Data In Setup and Hold Timing Diagram AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Data Valid...

  • Page 380: Figure 9-6. Video Input Port Timing Diagram

    VPCKIN fall/rise time VPCK_FR VPCKIN duty cycle VPCK_D Note 1. Guaranteed by characterization. VPCKIN PCK_FR VPD[7:0] Figure 9-6. Video Input Port Timing Diagram Unit 35/65 VP_C PCK_FR VP_S VP_H AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications Comments Note 1...

  • Page 381: Figure 9-7. Video Output Port Timing Diagram

    VOPCK fall/rise time VPCK_FR VOPCK duty cycle VPCK Note 1. Guaranteed by characterization. VOPCK VPCK_FR VOP[7:0] Figure 9-7. Video Output Port Timing Diagram AMD Geode™ SC1200/SC1201 Processor Data Book 40/60 VP_C VPCK_FR VP_V 32579B Unit Comments = 40 pF, Note 1...

  • Page 382: Figure 9-8. Tft Timing Diagram

    Note that signals DDC_SCL and DDC_SDA of the CRT interface are compliant with standard ACCESS.bus timing and are controlled by software. Table 9-15. TFT Timing Parameters 12.5 40/60 CLK_P Figure 9-8. TFT Timing Diagram AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications Unit Comments Note 1 CLK_RF...

  • Page 383: Table 9-16. Crt Vesa Compatible Dac (Red, Green, And Blue Outputs)

    Note 6. AV changes within the range of 3V to 3.6V. Output voltage is measured for peak-to-peak maximum change. CCRT PSSR is the ratio of the measurement of output at AV AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Unit Comments 0.72...

  • Page 384: Table 9-17. Tv Dac (4 Outputs: Cvbs, Svy/Tvr, Svc/Tvb, Cvbs/Tvg)

    Digital input = 3FFh 32.9 36.4 TVRSET to GND = 1140Ω = 37.5 Digital input = 3FFh ±1.5 Note 1 ±1.5 Note 2 1.17 1.29 Typically 1.235V ±5 KΩ Note 3 Note 4 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications...

  • Page 385: Table 9-18. Access.bus Input Timing Parameters

    Data high setup time DHCso Data low setup time DLCso AB1D/AB2D signal fall SCLfo time AB1D/AB2D signal rise SCLro time AMD Geode™ SC1200/SC1201 Processor Data Book SCLhigho SCLri SCLri SCLri - 1 μs - 1 μs SCLhigho SCLhigho SCLhigho SCLhigho...

  • Page 386: Figure 9-9. Acb Signals: Rising And Falling Timing Diagram

    Figure 9-10. ACB Start and Stop Condition Timing Diagram SCLfo 0.7V 0.3V SDAr 0.7V 0.3V SCLr Stop Condition Start Condition CSTOsi BUFi CSTOso BUFo AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications Unit Comments μs After AB1C/AB2C falling edge After AB1C/AB2C falling edge SDAf SCLf CSTRhi CSTRho...

  • Page 387: Figure 9-11. Acb Start Condition Timing Diagram

    AB2D AB1C AB2C Figure 9-11. ACB Start Condition TIming Diagram AB1D AB2D AB1C AB2C SDAvo SDAho Figure 9-12. ACB Data Bit Timing Diagram AMD Geode™ SC1200/SC1201 Processor Data Book Start Condition DHCsi CSTRsi CSTRhi DHCso CSTRso CSTRho SDAsi SDAso SCLlowi...

  • Page 388: Figure 9-13. Testing Setup For Pci Slew Rate And Minimum Timing

    -32V 26.7V Equation B (Figure 9-14) -25+(V +1)/0.015 25+(V -1)/0.015 0.5" max. Ω 10 pF AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications Unit Comments ≤ 0.3V 0 < V 0.3V < V < 0.9V 0.7V < V < V = 0.7V...

  • Page 389: Figure 9-14. V/I Curves For Pci Output Signals

    -12V -0.5 Equation A = (98.0/V )*(V )*(V for V >V >0.7V Figure 9-14. V/I Curves for PCI Output Signals AMD Geode™ SC1200/SC1201 Processor Data Book Output Voltage Volts Test Point Drive Point Drive Point -48V +0.4V = (256/V 32579B Pull-Down 0.5V...

  • Page 390: Figure 9-15. Pciclk Timing And Measurement Points

    0.5 V 0.4 V PCICLK 0.3 V Figure 9-15. PCICLK Timing and Measurement Points Table 9-21. PCI Clock Parameters 0.6V 0.2V HIGH AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications Unit Comments Note 1 Note 2 Note 2 V/ns Note 3...

  • Page 391: Figure 9-16. Load Circuits For Pci Maximum Time Measurements

    Note 6. All output drivers are asynchronously floated when PCIRST# is active. (Max) Rising Edge 0.5" max. Output Buffer Ω Figure 9-16. Load Circuits for PCI Maximum Time Measurements AMD Geode™ SC1200/SC1201 Processor Data Book Table 9-22. PCI Timing Parameters Output Buffer 10 pF 32579B Unit...

  • Page 392: Figure 9-17. Pci Output Timing Measurement Conditions

    0.4 V 0.285 V 0.615 V 0.4 V V/ns of overdrive. Timing parameters must not exceed this overdrive. TEST STEP Output Current ≤ Leakage Current AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications Comments Note 1 Note 1 Note 2...

  • Page 393: Figure 9-18. Pci Input Timing Measurement Conditions

    TRI_STATE Note: The value of t is 500 ns (maximum) from the power rail which exceeds specified tolerance by more than FAIL 500 mV. AMD Geode™ SC1200/SC1201 Processor Data Book TEST Input Valid TEST RST-CLK Figure 9-19. PCI Reset Timing...

  • Page 394: Table 9-24. Sub-Isa Timing Parameters

    Type (ns) M, I/O M, I/O 8, 16 M, I/O M, I/O 8, 16 8, 16 M, I/O M, I/O AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications (ns) Figure Comments 9-20 Standard 9-20 Zero wait state 9-20 Standard 9-20...
  • Page 395 MEMW#/DOCW#/IOW# inactive Write data D[15:0] after MEMW#/DOCW#/IOW# inactive Write data D[15:0] goes TRI-STATE after MEMW#/DOCW#/IOW# inactive Write data D[15:0] after read WDAR MEMR#/DOCR#/IOR# AMD Geode™ SC1200/SC1201 Processor Data Book Width (Bits) Type (ns) (ns) M, I/O 8, 16 M, I/O...

  • Page 396: Figure 9-20. Sub-Isa Read Operation Timing Diagram

    (Read) D[15:0] (Write) IOCHRDY RDYAx Note: x indicates a numeric index for the relevant symbol. Figure 9-20. Sub-ISA Read Operation Timing Diagram IOCSA IOCSH Valid RVDS Valid Data RDYH AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications Valid RCUx WDAR...

  • Page 397: Figure 9-21. Sub-Isa Write Operation Timing Diagram

    IOW#/WR# MEMW#/DOCW# TRDE# D[15:0] IOCHRDY IOR#/RD# MEMR#/DOCR# Note: x indicates a numeric index for the relevant symbol. Figure 9-21. Sub-ISA Write Operation Timing Diagram AMD Geode™ SC1200/SC1201 Processor Data Book IOCSA Valid Valid Data RDYAx RDYH 32579B IOCSH Valid WCUx...

  • Page 398: Figure 9-22. Lpc Output Timing Diagram

    PCICLK LPC Signals/ SERIRQ Table 9-25. LPC and SERIRQ Input Valid Figure 9-23. LPC Input Timing Diagram AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications Unit Comments After PCICLK rising edge After PCICLK rising edge After PCICLK rising edge Before PCICLK rising edge...

  • Page 399: Figure 9-24. Ide Reset Timing Diagram

    Parameter IDE signals fall time (from 0.9V IDE_FALL IDE signals rise time (from 0.1V IDE_RISE IDE_RST# pulse width IDE_RST_PW IDE_RST# AMD Geode™ SC1200/SC1201 Processor Data Book to 0.1V to 0.9V IDE_RST_PW Figure 9-24. IDE Reset Timing Diagram 32579B Unit Comments...

  • Page 400: Table 9-27. Ide Register Transfer To/From Device Timing Parameters

    The minimum total cycle time and t . (This means that a host implementation can lengthen t ) of IDE_IOR[0:1]# or IDE_IOW[0:1]#, then is met and t is not applicable. AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications Unit Comments Note 1 Note 1...

  • Page 401: Figure 9-25. Register Transfer To/From Device Timing Diagram

    The cycle completes after IDE_IORDY[0:1] is reasserted. For cycles where a wait is generated and IDE_IOR[0:1] is asserted, the device places read data on IDE_DATA[15:0] for t Figure 9-25. Register Transfer to/from Device Timing Diagram AMD Geode™ SC1200/SC1201 Processor Data Book from the assertion of IDE_IOR[0:1]# or IDE_IOW[0:1]#. but causes IDE_IORDY[0:1] to be asserted before t .

  • Page 402: Table 9-28. Ide Pio Data Transfer To/From Device Timing Parameters

    The minimum total cycle time and t . (This means that a host implementation may lengthen t is met and t is not applicable. AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications Unit Comments Note 1 Note 1...

  • Page 403: Figure 9-26. Pio Data Transfer To/From Device Timing Diagram

    IDE_DATA[15:0] for t Figure 9-26. PIO Data Transfer to/from Device Timing Diagram AMD Geode™ SC1200/SC1201 Processor Data Book from the assertion of IDE_IOR[0:1]# or IDE_IOW[0:1]#. but causes IDE_IORDY[0:1] to be asserted before t .

  • Page 404: Table 9-29. Ide Multiword Dma Data Transfer Timing Parameters

    . (This means that a host implementation can lengthen t KR/KW is equal to or greater than the value reported in the device’s IDENTIFY DEVICE AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications Unit Comments Note 1...

  • Page 405: Figure 9-27. Multiword Dma Data Transfer Timing Diagram

    IDE_DREQ[0:1] asserted and wait for the host to reasse IDE_DACK[0:1]#. This signal can be negated by the host to Suspend the DMA transfer in process. Figure 9-27. Multiword DMA Data Transfer Timing Diagram AMD Geode™ SC1200/SC1201 Processor Data Book 32579B...

  • Page 406: Table 9-30. Ide Ultradma Data Burst Timing Parameters

    Mode 0 Mode 1 is an unlimited interlock with no maximum time value. t is a limited time-out with a defined maximum. AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications Mode 2 Unit Comments...

  • Page 407: Figure 9-28. Initiating An Ultradma Data In Burst Timing Diagram

    (DSTROBE[0:1]) signal lines are not in effect until IDE_REQ[0:1] and IDE_DACK[0:1]# are asserted. Figure 9-28. Initiating an UltraDMA Data in Burst Timing Diagram AMD Geode™ SC1200/SC1201 Processor Data Book after the negation of DMARDY. Both STROBE and DMARDY timing measurements...

  • Page 408: Figure 9-29. Sustained Ultradma Data In Burst Timing Diagram

    Figure 9-29. Sustained UltraDMA Data In Burst Timing Diagram 2CYC 2CYC AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications...

  • Page 409: Figure 9-30. Host Pausing An Ultradma Data In Burst Timing Diagram

    IDE_IOR[0:1]# (HDMARDY[0:1]#) is de-asserted. If the t timing is not satisfied, the host may receive up to two additional data WORDs from the device. Figure 9-30. Host Pausing an UltraDMA Data In Burst Timing Diagram AMD Geode™ SC1200/SC1201 Processor Data Book 32579B...

  • Page 410: Figure 9-31. Device Terminating An Ultradma Data In Burst Timing Diagram

    Note: The definitions for the IDE_IOW[0:1]# (STOP[0:1]#), IDE_IOR[0:1]# (HDMARDY[0:1]#), and IDE_IRDY[0:1] (DSTROBE[0:1]) signal lines are no longer in effect after IDE_DREQ[0:1] and IDE_DACK[0:1]# are de-asserted. Figure 9-31. Device Terminating an UltraDMA Data In Burst Timing Diagram AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications IORDZ...

  • Page 411: Figure 9-32. Host Terminating An Ultradma Data In Burst Timing Diagram

    Note: The definitions for the IDE_IOW[0:1]# (STOP[0:1]#), IDE_IOR[0:1]# (HDMARDY[0:1]#), and IDE_IRDY[0:1] (DSTROBE[0:1]) signal lines are no longer in effect after IDE_DREQ[0:1] and IDE_DACK[0:1] are de-asserted. Figure 9-32. Host Terminating an UltraDMA Data In Burst Timing Diagram AMD Geode™ SC1200/SC1201 Processor Data Book IORDYZ 32579B...

  • Page 412: Figure 9-33. Initiating An Ultradma Data Out Burst Timing Diagram

    Note: The definitions for the IDE_IOW[0:1]]# (STOP[0:1]#), IDE_IORDY[0:1]# (DDMARDY[0:1]) and IDE_IOR[0:1]# (HSTROBE[0:1]#) signal lines are not in effect until IDE_DREQ[0:1] and IDE_DACK[0:1]# are asserted. Figure 9-33. Initiating an UltraDMA Data Out Burst Timing Diagram ZIORDY AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications...

  • Page 413: Figure 9-34. Sustained Ultradma Data Out Burst Timing Diagram

    Figure 9-34. Sustained UltraDMA Data Out Burst Timing Diagram AMD Geode™ SC1200/SC1201 Processor Data Book 2CYC 2CYC...

  • Page 414: Figure 9-35. Device Pausing An Ultradma Data Out Burst Timing Diagram

    IDE_IORDY[0:1]# (DDMARDY[0:1]#) is de-asserted. If the t timing is not satisfied, the device may receive up to two additional datawords from the host. Figure 9-35. Device Pausing an UltraDMA Data Out Burst Timing Diagram AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications after...

  • Page 415: Figure 9-36. Host Terminating An Ultradma Data Out Burst Timing Diagram

    Note: The definitions for the IDE_IOW[0:1]# (STOP[0:1]#), IDE_IORDY[0,1]# (DDMARDY[0:1]#) and IDE_IOR[0:1]# (HSTROBE[0:1]#) signal lines are no longer in effect after IDE_DREQ[0:1] and IDE_DACK[0:1]# are de-asserted. Figure 9-36. Host Terminating an UltraDMA Data Out Burst Timing Diagram AMD Geode™ SC1200/SC1201 Processor Data Book 32579B IORDYZ...

  • Page 416: Figure 9-37. Device Terminating An Ultradma Data Out Burst Timing Diagram

    Note: The definitions for the IDE_IOW[0:1]# (STOP[0:1]#), IDE_IORDY[0:1]# (DDMARDY[0:1]#) and IDE_IOR[0:1]# (HSTROBE[0:1]#) signal lines are no longer in effect after IDE_DREQ[0:1] and IDE_DACK[0:1]# are de-asserted. Figure 9-37. Device Terminating an UltraDMA Data Out Burst Timing Diagram IORDZ AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications...

  • Page 417: Universal Serial Bus (Usb)

    Source differential driver jitter for con- USB_DJD21 secutive transactions Source differential driver jitter for paired USB_DJD22 transactions Source differential driver jitter for con- USB_DJU21 secutive transaction AMD Geode™ SC1200/SC1201 Processor Data Book Table 9-31. USB Timing Parameters 11.97 12.03 Mbps 0.9995 1.0005 83.1 83.5 –3.5...
  • Page 418 9-41 –45 9-41 9-39 9-39 ) to ground. = DNEG_PORT = SE0. SE0 occurs when output level voltage ≤ AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications Function (downstream), Note 4 Note 4, Note 5 Note 5 Host (upstream), Note 4...

  • Page 419: Figure 9-38. Usb Data Signal Rise And Fall Timing Diagram

    Figure 9-38. USB Data Signal Rise and Fall Timing Diagram period_F period_L Differential Data Lines Consecutive Transitions period period_L period_L Figure 9-39. USB Source Differential Data Jitter Timing Diagram AMD Geode™ SC1200/SC1201 Processor Data Book Differential Data Lines = 350 pF USB_DJ11 USB_DJD21 USB_DJU21 Crossover Points (1.3-2.0) V USB_DJ11...

  • Page 420: Figure 9-40. Usb Eop Width Timing Diagram

    Level Source: USB_SE1, USB_DE1 Receiver: USB_DE2 USB_RE11, USB_RE21, EOP Width USB_RJ11 USB_RJD21 USB_RJU21 Crossover Points USB_RJ11 USB_RJD21 USB_RJU21 Paired Transitions period_F USB_RJ12 period_L USB_RJD22 period_L USB_RJU22 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications USB_SE2 USB_RE12 USB_RE22 USB_RJ12 USB_RJD22 USB_RJU22...

  • Page 421: Serial Port (Uart)

    RXHSC bit (bit 5) of the RCCFG register. UART Sharp IR Consumer Remote Control Figure 9-42. UART, Sharp-IR, SIR, and Consumer Remote Control Timing Diagram AMD Geode™ SC1200/SC1201 Processor Data Book - 25 + 25 (Note 1) - 2% + 2% - 25...

  • Page 422: Figure 9-43. Fast Ir Timing (Mir And Fir) Diagram

    01h in bank 6 of logical device 5. Figure 9-43. Fast IR Timing (MIR and FIR) Diagram (Note 1) ± 0.1% ± 2.9% ± 0.01% ± 4.0% Data Symbol FDPW Chips AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications Unit Comments Transmitter Receiver Transmitter Receiver Transmitter Receiver...

  • Page 423: Figure 9-44. Standard Parallel Port Typical Data Exchange Timing Diagram

    Note 1. Times are system dependent and are therefore not tested. BUSY ACK# PD[7:0] STB# Figure 9-44. Standard Parallel Port Typical Data Exchange Timing Diagram AMD Geode™ SC1200/SC1201 Processor Data Book 32579B Unit Comments Note 1 Note 1 Note 1...

  • Page 424: Figure 9-45. Enhanced Parallel Port Timing Diagram

    PD[7:0] hold after DSTRB# or EPDH ASTRB# inactive WW19a WRITE# DSTRB# ASTRB# WST19a PD[7:0] WPDS WAIT# Figure 9-45. Enhanced Parallel Port Timing Diagram WPDH WEST WW19ia AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications Unit Comments WST19a EPDH Valid EPDW...

  • Page 425: Figure 9-46. Ecp Forward Mode Timing Diagram

    STB# inactive after BUSY active ECHHF BUSY inactive after STB# active ECHLF STB# active after BUSY inactive ECLLF PD[7:0] AFD# STB# BUSY Figure 9-46. ECP Forward Mode Timing Diagram AMD Geode™ SC1200/SC1201 Processor Data Book ECDHF ECDSF ECHLF ECLHF ECHHF 32579B Unit Comments ECLLF...

  • Page 426: Figure 9-47. Ecp Reverse Mode Timing Diagram

    ECHHR AFD# active after ACK# inactive ECHLR ACK# active after AFD# active ECLLR PD[7:0] BUSY# ACK# AFD# Figure 9-47. ECP Reverse Mode Timing Diagram ECDSR ECHLR ECLHR ECHHR AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications Unit Comments ECDHR ECLLR...

  • Page 427: Figure 9-48. Ac97 Reset Timing Diagram

    Table 9-39. AC97 Sync Timing Parameters Symbol Parameter SYNC active high pulse width SYNC_HIGH SYNC inactive to BIT_CLK startup SYNC_IA delay SYNC BIT_CLK Figure 9-49. AC97 Sync Timing Diagram AMD Geode™ SC1200/SC1201 Processor Data Book 162.8 RST2CLK RST_LOW 162.8 SYNC_IA SYNC_HIGH 32579B Unit Comments µs...

  • Page 428: Figure 9-50. Ac97 Clocks Diagram

    48.0 20.8 19.5 24.576 40.7 CLK_L CLK_H CLK_PD SYNC_L SYNC_H SYNC_PD AC97_CLK_PD AC97_CLK_FR Figure 9-50. AC97 Clocks Diagram AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications Unit Comments Note 1 Note 1 µs µs µs Measured from edge to edge...

  • Page 429: Figure 9-51. Ac97 Data Timing Diagram

    Sync out valid after rising edge of AC97_SV BIT_CLK Sync out hold after falling edge of AC97_SH BIT_CLK BIT_CLK SDATA_OUT/SYNC SDATA_IN, SDATA_IN2 AMD Geode™ SC1200/SC1201 Processor Data Book Table 9-41. AC97 I/O Timing Parameters 15.0 10.0 AC97_SV AC97_OV AC97_S AC97_H Figure 9-51. AC97 Data TIming Diagram...

  • Page 430: Figure 9-52. Ac97 Rise And Fall Timing Diagram

    Figure 9-52. AC97 Rise and Fall Timing Diagram Unit trise tfall trise tfall SYNC SYNC trise tfall trise tfall DOUT DOUT AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications Comments = 50 pF = 50 pF = 50 pF = 50 pF...

  • Page 431: Figure 9-53. Ac97 Low Power Mode Timing Diagram

    End of Slot 2 to BIT_CLK, s2_pdown SDATA_IN low SYNC BIT_CLK SDATA_OUT SDATA_IN Note: BIT_CLK is not to scale Figure 9-53. AC97 Low Power Mode Timing Diagram AMD Geode™ SC1200/SC1201 Processor Data Book Unit µs Slot 1 Slot 2 s2_pdown 32579B Comments...

  • Page 432: Figure 9-54. Pwrbtn# Trigger And Onctl# Timing Diagram

    Table 9-45. Power Management Event (GPWIO) and ONCTL# Timing Parameters Symbol Parameter Power management event to ONCTL# assertion GPWIOx ONCTL# PWRCNT1 PWRCNT2 Figure 9-55. GPWIO and ONCTL# Timing Diagram Unit PBTNP PBTNE PBTNE Unit AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications Comments Note 1 PBTNP Comments...

  • Page 433: Figure 9-56. Power-Up Sequencing With Pwrbtn# Timing Diagram

    POR# inactive after V CORE applied CORE PWRBTN# ONTCL# PWRCNT[2:1] POR# Figure 9-56. Power-Up Sequencing With PWRBTN# Timing Diagram AMD Geode™ SC1200/SC1201 Processor Data Book -100 or V 4000 applied and V 32579B Unit Comments Optimum power-up results with = 0.

  • Page 434: Figure 9-57. Power-Up Sequencing Without Pwrbtn# Timing Diagram

    Asserting POR# has no effect on ACPI. If POR# is asserted and ACPI was active prior to POR#, then ACPI will remain active after POR#. Therefore, BIOS must ensure that ACPI is inactive before GPIO63 is pulsed low. -100 CORE AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications Unit Comments Optimum power-up results with = 0.

  • Page 435: Jtag Interface

    Non-test inputs setup time TDI, TMS hold time Non-test inputs hold time IH(Min) 1.5V IL(Max) Figure 9-58. TCK Measurement Points and Timing Diagram AMD Geode™ SC1200/SC1201 Processor Data Book Table 9-48. JTAG Timing Parameters 32579B Unit Comments 50 pF load...

  • Page 436: Figure 9-59. Jtag Test Timing Diagram

    32579B TDI, Output Signals Input Signals Figure 9-59. JTAG Test Timing Diagram AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications...

  • Page 437: 10.0Package Specifications

    (Nominal) Frequency Power (W) 1.8V 266 MHz AMD Geode™ SC1200/SC1201 Processor Data Book 10.0Package Specifications ) of the pack- A maximum junction temperature is not specified since a maximum case temperature is. Therefore, the following equation can be used to calculate the maximum thermal...

  • Page 438: Figure 10-1. Heatsink Example

    Note: The power dissipations P used in these examples are not representative of the power dissipation of the SC1200/SC1201 processor, which is always less than 4 Watts. CA = 45/9 = 5 AMD Geode™ SC1200/SC1201 Processor Data Book Package Specifications (max) = 40°C. − T 85 − 40 =8).

  • Page 439: Physical Dimensions

    Package Specifications 32579B 10.2 Physical Dimensions The figures in this section provide the mechanical package outlines for the BGU481 (481-Terminal Ball Grid Array Cavity Up) package. Figure 10-2. BGU481 Package - Top View AMD Geode™ SC1200/SC1201 Processor Data Book...

  • Page 440: Figure 10-3. Bgu481 Package - Bottom View

    32579B Package Specifications Figure 10-3. BGU481 Package - Bottom View AMD Geode™ SC1200/SC1201 Processor Data Book...

  • Page 441: A.1 Order Information

    The “B” suffix denotes a maximum I Table 9-7 on page 369 for details. Consult your local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations possibly not listed. Macrovision Product Notice The SC1201 processor is protected by U.S.

  • Page 442: Data Book Revision History

    32579B Data Book Revision History This section is a report of the revision/creation process of the data book for the AMD Geode™ SC1200/SC1201 processor. Any revisions (i.e., additions, deletions, parameter corrections, etc.) are recorded in the table(s) below. Revision #...
  • Page 443 One AMD Place • P.O. Box 3453 • Sunnyvale, CA 94088-3453 USA • Tel: 408-749-4000 or 800-538-8450 • TWX: 910-339-9280 • TELEX: 34-6306...

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