AMD SB600 Technical Reference Manual page 16

Register reference manual
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Field Name
Note: This field is only writeable when PCI_Reg:40h[0] is set.
Sub-Class Code
Program Interface Controller Type
01
8F
06
01
04
00
Field Name
Reserved
Cache Line Size Register
Field Name
Reserved
Master Latency Timer
Field Name
Header Type
Field Name
Completion Code
Reserved
Start BIST
BIST Capable
Field Name
Resource Type Indicator
Reserved
Primary IDE CS0 Base
Address
Field Name
Resource Type Indicator
Reserved
Primary IDE CS1 Base
Address
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Revision ID/Class Code- R - 32 bits - [PCI_Reg:08h]
Bits
Default
IDE
AHCI
RAID
Cache Line Size - RW - 8 bits - [PCI_Reg:0Ch]
Bits
Default
3:0
Reserved.
7:4
0h
If the value is 1, then the cache line size is 16 DW (64 byte).
Master Latency Timer - RW - 8 bits - [PCI_Reg:0Dh]
Bits
Default
2:0
Reserved.
7:3
00h
Master Latency Timer. This number, in units of clocks,
represents the guaranteed time slice allowed to the IDE host
controller for burst transactions.
Header Type - R - 8 bits - [PCI_Reg:0Eh]
Bits
Default
7:0
00h
Header Type. Since the IDE host controller is a single-function
device, this register contains a value of 00h.
BIST Mode Type - RW - 8 bits - [PCI_Reg:0Fh]
Bits
Default
3:0
0h
Read Only.
Indicates the completion code status of BIST. A non-zero
value indicates a failure.
5:4
Reserved.
6
0b
Since bit [7] is 0, program this bit take no effect.
7
0b
Read Only. Hard-wired to '0' indicating that there is no HBA
related BIST function.
Base Address 0 - RW - 32 bits - [PCI_Reg:10h]
Bits
Default
0
1b
RTE (Resource Type Indicator). This bit is wired to 1 to
indicate that the base address field in this register maps to I/O
space.
2:1
Reserved.
31:3
0000_
Base Address for Primary IDE Bus CS0. This register is used
0000h
for native mode only. Base Address 0 is not used in
compatibility mode.
Base Address 1 - RW - 32 bits - [PCI_Reg:14h]
Bits
Default
0
1b
RTE (Resource Type Indicator). This bit is wired to 1 to
indicate that the base address field in this register maps to I/O
space.
1
Reserved.
31:2
0000_
Base Address for Primary IDE Bus CS1. This register is used
0000h
for native mode only. Base Address 1 is not used in
compatibility mode.
Description
Description
Description
Description
Description
Description
Description
SATA Registers (Device 18, Function 0)
Proprietary
Page 16

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