AMD SB600 Technical Reference Manual page 177

Field Name
Reserved
PciExpWakeDis
Reserved
This register is located at the base address defined by AcpiPmEvtBlk.
Field Name
SCI_EN
BmRld
GBL_RLS
Reserved
SlpType
SlpEn
Reserved
This register is located at the base address defined by AcpiPm1CntBlk.
Field Name
ARB_DIS
Reserved
This register is located at the base address defined by AcpiPmaCntBlk.
TmrValue/ETmrValue – R - 32 bits - [AcpiPmTmrBlk:00h]
Field Name
TmrValue
This register is located at the base address defined by AcpiPmTmrBlk.
Field Name
Reserved
ClkValue
ThtEn
Reserved
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Pm1Enable - RW - 16 bits - [AcpiPmEvtBlk:02h]
Bits Default
13:11 000b
14 1b This bit disables the inputs to the PciExpWakeStatus from
waking the system.
15 0b
PmControl - RW - 16 bits - [AcpiPm1CntBlk:00h]
Bits Default
0 0b Selects the power management event to be either an SCI or
SMI# interrupt for the following events. When this bit is set,
then PM events will generate an SCI interrupt; otherwise, it
will be SMI#.
1 0b If this bit is set, SCI is raised whenever there is a bus master
active
2 0b If PM IO x0E bit[0] is set, writing 1 to this bit will generate
SMI# and set PM IO x0F bit[0]. This bit will always return 0.
9:3 00h
12:10 000b Defines the sleep state the system enters when the SlpEn is
set to one. This design currently implements 3 states: S1,
S3, and S5
13 0b This is a write-only bit and reads from it always return zero.
If PM_Reg 04h bit7 SLP_SMI_EN is 0, setting this bit causes
the system to sequence into the sleeping state associated
with the SlpType fields programmed. If SLP_SMI_EN is 1,
setting this bit causes SMI#. Writing 0 to this bit has no
effect. This applies to both P4 and K8 systems.
15:14 00b
PmaControl - RW - 8 bits - [AcpiPmaCntBlk:00h]
Bits Default
0 0b System arbiter is disabled when this bit is set.
7:1 00h
Bits Default
31:0 - This read-only field returns the running count of the power
management timer.
CLKVALUE - RW - 32 bits - [CpuControl:00h]
Bits Default
0 0b
3:1 000b These bits define throttle interval for STPCLK# de-assertion
000b: 50%
001b: 12.5%
010b: 25%
011b: 37.5%
100b: 50%
101b: 62.5%
110b: 75%
111b: 87.5%
4 0b This bit enables clock throttling as set in the ClkValue.
31:5 0000000h
Description
Description
Description
Description
Description
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary Page 177