Pathbuilder S700 Architecture - 3Com 3C63400-3AC-C - PathBuilder S700 Switch Reference Manual

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HAPTER YSTEM ESCRIPTION
PathBuilder S700
Architecture
The STX module provides the following features:
Any-to-any port switching
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Virtual interfaces (VIs); logical UNI ports that provide traffic shaping profiles
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(127 total VIs allowed: 24 per triple-slot bus (7-9, 10-12, 13-15, 16-18), 15 per
slot for slots 5 and 6, 1 for MCPU)
Deep buffers for queuing (8,000 cells per VI for a total of over 1 million cells
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buffered per shelf)
Priority queuing in which each VI can be assigned to specific VCs which can be
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allocated to one of 4 queues
Per VC traffic policing
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Multicasting (up to 256 connections with 32 leaves)
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Bipolar Timing Source (BITS) timing clock
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Per VC statistics
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4,000 connections per unit
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The modular architecture of the PathBuilder S700 is designed to accommodate a
wide range of interfaces and support a comprehensive set of applications. The
core component of the unit is a 3.2 Gbps cell bus backplane where all traffic is
carried in the form of ATM cells. The PathBuilder S700 accommodates up to six
power supplies (AC 110/220 VAC and DC-48 VDC) in a load-sharing
configuration.
The overall design philosophy of the PathBuilder S700 is to facilitate the transfer of
cells on and off the bus backplane with enhanced traffic management and
switching capabilities. Figure 1 illustrates the cell bus architecture. All
packet-to-cell segmentation and reassembly (SAR) functions are performed on
each of the application modules (Ethernet, Frame Relay, and CBR), thereby
ensuring efficient cell transfer through the system. Additional SAR power is added
each time a non-ATM interface module is added.
Figure 1 PathBuilder S700 Cell Bus Architecture
10BaseT(2) V.35(4), HSSI(1), T1(8)
Ethernet
STX
T1/E1(4/8)
Frame
CBR
Relay
10BaseT,RS232, SLIP
T1/E1(with integral IMA),
DS3/E3, OC3/STM-1
ATM
MCPU