Omron CP - PROGRAMMING MANUAL 05-2007 Programming Manual page 42

Cp1h/cp1l cpu unit
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Programming Concepts
Operand
Specifying
The offset from the beginning of the area is
indirect DM
specified. The contents of the address will be
addresses in
treated as BCD data (0000 to 9999) to specify
BCD Mode
the word address in Data Memory (DM). Add
an asterisk (*) at the front to specify an indirect
address in BCD Mode.
Contents
D
Specifying a
An index register (IR) or a data register (DR) is
register
specified directly by specifying IR@ (@: 0 to
directly
15) or DR@ (@: 0 to 15).
Operand
Specifying
Indirect
an indirect
address
address
(No offset)
using a reg-
ister
Constant
offset
Description
*D@@@@@
00000 to 9999
(BCD)
Description
The bit or word with the PLC memory
address contained in IR@ will be speci-
fied.
Specify ,IR@ to specify bits and words
for instruction operands.
The bit or word with the PLC memory
address in IR@ + or – the constant is
specified.
Specify +/– constant ,IR@. Constant off-
sets range from –2048 to +2047 (deci-
mal). The offset is converted to binary
data when the instruction is executed.
Notation
*D200
Contents
0 1 0 0
BCD: 100
Specifies D100.
Add an asterisk (*).
IR0
IR1
Notation
Application examples
,IR0
,IR0
Loads the bit with the PLC memory
address in IR0.
,IR1
MOV(021)
#1
,IR1
Stores #0001 in the word with the PLC
memory in IR1.
+5,IR0
+5,IR0
Loads the bit with the PLC memory
address in IR0 + 5.
+31,IR1
MOV(021)
#1
+31 ,IR1
Stores #0001 in the word with the PLC
memory address in IR1 + 31
Section 1-1
Application
examples
MOV(021)
#1
*D200
MOVR(560)
1.02
IR0
Stores the PLC
memory
address for
CIO 10 in IR0.
MOVR(560)
10
IR1
Stores the PLC
memory
address for
CIO 10 in IR1.
9

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